Commit d25cf2c7 authored by Jack Xu's avatar Jack Xu Committed by Herbert Xu

crypto: qat - add next neighbor to chip_info

Introduce the next neighbor (NN) capability in chip_info as NN registers
are not supported in certain SKUs of QAT.
Signed-off-by: default avatarJack Xu <jack.xu@intel.com>
Co-developed-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 49c13273
...@@ -24,6 +24,7 @@ struct icp_qat_fw_loader_hal_handle { ...@@ -24,6 +24,7 @@ struct icp_qat_fw_loader_hal_handle {
struct icp_qat_fw_loader_chip_info { struct icp_qat_fw_loader_chip_info {
bool sram_visible; bool sram_visible;
bool nn;
bool fw_auth; bool fw_auth;
}; };
......
...@@ -603,7 +603,9 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) ...@@ -603,7 +603,9 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);
csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
csr_val &= IGNORE_W1C_MASK; csr_val &= IGNORE_W1C_MASK;
csr_val |= CE_NN_MODE; if (handle->chip_info->nn)
csr_val |= CE_NN_MODE;
qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val); qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);
qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst), qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),
(u64 *)inst); (u64 *)inst);
...@@ -665,10 +667,12 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, ...@@ -665,10 +667,12 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
case PCI_DEVICE_ID_INTEL_QAT_C62X: case PCI_DEVICE_ID_INTEL_QAT_C62X:
case PCI_DEVICE_ID_INTEL_QAT_C3XXX: case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
handle->chip_info->sram_visible = false; handle->chip_info->sram_visible = false;
handle->chip_info->nn = true;
handle->chip_info->fw_auth = true; handle->chip_info->fw_auth = true;
break; break;
case PCI_DEVICE_ID_INTEL_QAT_DH895XCC: case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
handle->chip_info->sram_visible = true; handle->chip_info->sram_visible = true;
handle->chip_info->nn = true;
handle->chip_info->fw_auth = false; handle->chip_info->fw_auth = false;
break; break;
default: default:
...@@ -1433,6 +1437,11 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle, ...@@ -1433,6 +1437,11 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
{ {
int stat = 0; int stat = 0;
unsigned char ctx; unsigned char ctx;
if (!handle->chip_info->nn) {
dev_err(&handle->pci_dev->dev, "QAT: No next neigh in 0x%x\n",
handle->pci_dev->device);
return -EINVAL;
}
if (ctx_mask == 0) if (ctx_mask == 0)
return -EINVAL; return -EINVAL;
......
...@@ -884,11 +884,13 @@ static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle, ...@@ -884,11 +884,13 @@ static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle,
pr_err("QAT: qat_hal_set_ae_ctx_mode error\n"); pr_err("QAT: qat_hal_set_ae_ctx_mode error\n");
return ret; return ret;
} }
mode = ICP_QAT_NN_MODE(uof_image->ae_mode); if (handle->chip_info->nn) {
ret = qat_hal_set_ae_nn_mode(handle, ae, mode); mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
if (ret) { ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
pr_err("QAT: qat_hal_set_ae_nn_mode error\n"); if (ret) {
return ret; pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
return ret;
}
} }
mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode); mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode);
ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode); ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode);
......
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