Commit d28be499 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo

ARM: dts: imx6qdl-sabresd: Allow HDMI and LVDS to work simultaneously

Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.

Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.

With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Acked-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent fb00ff4c
......@@ -141,6 +141,13 @@ &audmux {
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
......
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