Commit d461e96c authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "These are all the driver updates for SoC specific drivers. There are a
  couple of subsystems with individual maintainers picking up their
  patches here:

   - The reset controller subsystem add support for a few new SoC
     variants to existing drivers, along with other minor improvements

   - The OP-TEE subsystem gets a driver for the ARM FF-A transport

   - The memory controller subsystem has improvements for Tegra,
     Mediatek, Renesas, Freescale and Broadcom specific drivers.

   - The tegra cpuidle driver changes get merged through this tree this
     time. There are only minor changes, but they depend on other tegra
     driver updates here.

   - The ep93xx platform finally moves to using the drivers/clk/
     subsystem, moving the code out of arch/arm in the process. This
     depends on a small sound driver change that is included here as
     well.

   - There are some minor updates for Qualcomm and Tegra specific
     firmware drivers.

  The other driver updates are mainly for drivers/soc, which contains a
  mixture of vendor specific drivers that don't really fit elsewhere:

   - Mediatek drivers gain more support for MT8192, with new support for
     hw-mutex and mmsys routing, plus support for reset lines in the
     mmsys driver.

   - Qualcomm gains a new "sleep stats" driver, and support for the
     "Generic Packet Router" in the APR driver.

   - There is a new user interface for routing the UARTS on ASpeed BMCs,
     something that apparently nobody else has needed so far.

   - More drivers can now be built as loadable modules, in particular
     for Broadcom and Samsung platforms.

   - Lots of improvements to the TI sysc driver for better
     suspend/resume support"

  Finally, there are lots of minor cleanups and new device IDs for
  amlogic, renesas, tegra, qualcomm, mediateka, samsung, imx,
  layerscape, allwinner, broadcom, and omap"

* tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (179 commits)
  optee: Fix spelling mistake "reclain" -> "reclaim"
  Revert "firmware: qcom: scm: Add support for MC boot address API"
  qcom: spm: allow compile-testing
  firmware: arm_ffa: Remove unused 'compat_version' variable
  soc: samsung: exynos-chipid: add exynosautov9 SoC support
  firmware: qcom: scm: Don't break compile test on non-ARM platforms
  soc: qcom: smp2p: Add of_node_put() before goto
  soc: qcom: apr: Add of_node_put() before return
  soc: qcom: qcom_stats: Fix client votes offset
  soc: qcom: rpmhpd: fix sm8350_mxc's peer domain
  dt-bindings: arm: cpus: Document qcom,msm8916-smp enable-method
  ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226
  firmware: qcom: scm: Add support for MC boot address API
  soc: qcom: spm: Add 8916 SPM register data
  dt-bindings: soc: qcom: spm: Document qcom,msm8916-saw2-v3.0-cpu
  soc: qcom: socinfo: Add PM8150C and SMB2351 models
  firmware: qcom_scm: Fix error retval in __qcom_scm_is_call_available()
  soc: aspeed: Add UART routing support
  soc: fsl: dpio: rename the enqueue descriptor variable
  soc: fsl: dpio: use an explicit NULL instead of 0
  ...
parents ae45d84f 6a035689
What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
Date: September 2021
Contact: Oskar Senft <osk@google.com>
Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Description: Selects the RX source of the UARTx device.
When read, each file shows the list of available options with currently
selected option marked by brackets "[]". The list of available options
depends on the selected file.
e.g.
cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
[io1] io2 io3 io4 uart2 uart3 uart4 io6
In this case, UART1 gets its input from IO1 (physical serial port 1).
Users: OpenBMC. Proposed changes should be mailed to
openbmc@lists.ozlabs.org
What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io*
Date: September 2021
Contact: Oskar Senft <osk@google.com>
Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Description: Selects the RX source of IOx serial port. The current selection
will be marked by brackets "[]".
Users: OpenBMC. Proposed changes should be mailed to
openbmc@lists.ozlabs.org
...@@ -211,6 +211,9 @@ properties: ...@@ -211,6 +211,9 @@ properties:
- qcom,gcc-msm8660 - qcom,gcc-msm8660
- qcom,kpss-acc-v1 - qcom,kpss-acc-v1
- qcom,kpss-acc-v2 - qcom,kpss-acc-v2
- qcom,msm8226-smp
# Only valid on ARM 32-bit, see above for ARM v8 64-bit
- qcom,msm8916-smp
- renesas,apmu - renesas,apmu
- renesas,r9a06g032-smp - renesas,r9a06g032-smp
- rockchip,rk3036-smp - rockchip,rk3036-smp
...@@ -297,7 +300,8 @@ properties: ...@@ -297,7 +300,8 @@ properties:
Specifies the ACC* node associated with this CPU. Specifies the ACC* node associated with this CPU.
Required for systems that have an "enable-method" property Required for systems that have an "enable-method" property
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
"qcom,msm8916-smp".
* arm/msm/qcom,kpss-acc.txt * arm/msm/qcom,kpss-acc.txt
......
...@@ -11,8 +11,9 @@ maintainers: ...@@ -11,8 +11,9 @@ maintainers:
properties: properties:
compatible: compatible:
items: enum:
- const: samsung,exynos4210-chipid - samsung,exynos4210-chipid
- samsung,exynos850-chipid
reg: reg:
maxItems: 1 maxItems: 1
......
* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
Required properties:
- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
"jedec,lpddr2-s4"
"ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
"ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
"ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
- density : <u32> representing density in Mb (Mega bits)
- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
Optional properties:
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
- tRRD-min-tck
- tWTR-min-tck
- tXP-min-tck
- tRTP-min-tck
- tCKE-min-tck
- tRPab-min-tck
- tRCD-min-tck
- tWR-min-tck
- tRASmin-min-tck
- tCKESR-min-tck
- tFAW-min-tck
Child nodes:
- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/
bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
Example:
elpida_ECB240ABACN : lpddr2 {
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
}
...@@ -102,7 +102,6 @@ examples: ...@@ -102,7 +102,6 @@ examples:
- | - |
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sc7180.h> #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
displayport-controller@ae90000 { displayport-controller@ae90000 {
......
...@@ -13,8 +13,10 @@ Required properties: ...@@ -13,8 +13,10 @@ Required properties:
* "qcom,scm-ipq806x" * "qcom,scm-ipq806x"
* "qcom,scm-ipq8074" * "qcom,scm-ipq8074"
* "qcom,scm-mdm9607" * "qcom,scm-mdm9607"
* "qcom,scm-msm8226"
* "qcom,scm-msm8660" * "qcom,scm-msm8660"
* "qcom,scm-msm8916" * "qcom,scm-msm8916"
* "qcom,scm-msm8953"
* "qcom,scm-msm8960" * "qcom,scm-msm8960"
* "qcom,scm-msm8974" * "qcom,scm-msm8974"
* "qcom,scm-msm8994" * "qcom,scm-msm8994"
...@@ -33,7 +35,7 @@ Required properties: ...@@ -33,7 +35,7 @@ Required properties:
* core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
"qcom,scm-msm8960" "qcom,scm-msm8960"
* core, iface and bus clocks required for "qcom,scm-apq8084", * core, iface and bus clocks required for "qcom,scm-apq8084",
"qcom,scm-msm8916" and "qcom,scm-msm8974" "qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974"
- clock-names: Must contain "core" for the core clock, "iface" for the interface - clock-names: Must contain "core" for the core clock, "iface" for the interface
clock and "bus" for the bus clock per the requirements of the compatible. clock and "bus" for the bus clock per the requirements of the compatible.
- qcom,dload-mode: phandle to the TCSR hardware block and offset of the - qcom,dload-mode: phandle to the TCSR hardware block and offset of the
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
oneOf:
- items:
- enum:
- elpida,ECB240ABACN
- elpida,B8132B2PB-6D-F
- enum:
- jedec,lpddr2-s4
- items:
- enum:
- jedec,lpddr2-s2
- items:
- enum:
- jedec,lpddr2-nvm
revision-id1:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 1 value of SDRAM chip. Obtained from device datasheet.
revision-id2:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 2 value of SDRAM chip. Obtained from device datasheet.
density:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Density in megabits of SDRAM chip. Obtained from device datasheet.
enum:
- 64
- 128
- 256
- 512
- 1024
- 2048
- 4096
- 8192
- 16384
- 32768
io-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
IO bus width in bits of SDRAM chip. Obtained from device datasheet.
enum:
- 32
- 16
- 8
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Active bank a to active bank b in terms of number of clock cycles.
Obtained from device datasheet.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
Obtained from device datasheet.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles. Obtained from device datasheet.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles. Obtained from device datasheet.
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles. Obtained from device datasheet.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Row precharge time (all banks) in terms of number of clock cycles.
Obtained from device datasheet.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
RAS-to-CAS delay in terms of number of clock cycles. Obtained from
device datasheet.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
WRITE recovery time in terms of number of clock cycles. Obtained from
device datasheet.
tRASmin-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Row active time in terms of number of clock cycles. Obtained from device
datasheet.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles. Obtained from device
datasheet.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Four-bank activate window in terms of number of clock cycles. Obtained
from device datasheet.
patternProperties:
"^lpddr2-timings":
type: object
description: |
The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/
bindings/memory-controllers/ddr/lpddr2-timings.txt for more information
on "lpddr2-timings".
required:
- compatible
- density
- io-width
additionalProperties: false
examples:
- |
elpida_ECB240ABACN: lpddr2 {
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
revision-id1 = <1>;
revision-id2 = <0>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
};
...@@ -43,8 +43,9 @@ These values shall be obtained from the device data-sheet. ...@@ -43,8 +43,9 @@ These values shall be obtained from the device data-sheet.
Child nodes: Child nodes:
- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". - The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
"lpddr3-timings" provides AC timing parameters of the device for "lpddr3-timings" provides AC timing parameters of the device for
a given speed-bin. Please see Documentation/devicetree/ a given speed-bin. Please see
bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
for more information on "lpddr3-timings"
Example: Example:
......
...@@ -16,7 +16,7 @@ description: | ...@@ -16,7 +16,7 @@ description: |
MediaTek SMI have two generations of HW architecture, here is the list MediaTek SMI have two generations of HW architecture, here is the list
which generation the SoCs use: which generation the SoCs use:
generation 1: mt2701 and mt7623. generation 1: mt2701 and mt7623.
generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192. generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195.
There's slight differences between the two SMI, for generation 2, the There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But register which control the iommu port is at each larb's register base. But
...@@ -36,6 +36,9 @@ properties: ...@@ -36,6 +36,9 @@ properties:
- mediatek,mt8173-smi-common - mediatek,mt8173-smi-common
- mediatek,mt8183-smi-common - mediatek,mt8183-smi-common
- mediatek,mt8192-smi-common - mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
- mediatek,mt8195-smi-sub-common
- description: for mt7623 - description: for mt7623
items: items:
...@@ -65,6 +68,10 @@ properties: ...@@ -65,6 +68,10 @@ properties:
minItems: 2 minItems: 2
maxItems: 4 maxItems: 4
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the smi-common node above. Only for sub-common.
required: required:
- compatible - compatible
- reg - reg
...@@ -91,6 +98,29 @@ allOf: ...@@ -91,6 +98,29 @@ allOf:
- const: smi - const: smi
- const: async - const: async
- if: # only for sub common
properties:
compatible:
contains:
enum:
- mediatek,mt8195-smi-sub-common
then:
required:
- mediatek,smi
properties:
clock:
items:
minItems: 3
maxItems: 3
clock-names:
items:
- const: apb
- const: smi
- const: gals0
else:
properties:
mediatek,smi: false
- if: # for gen2 HW that have gals - if: # for gen2 HW that have gals
properties: properties:
compatible: compatible:
...@@ -98,6 +128,8 @@ allOf: ...@@ -98,6 +128,8 @@ allOf:
- mediatek,mt6779-smi-common - mediatek,mt6779-smi-common
- mediatek,mt8183-smi-common - mediatek,mt8183-smi-common
- mediatek,mt8192-smi-common - mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
then: then:
properties: properties:
......
...@@ -24,6 +24,7 @@ properties: ...@@ -24,6 +24,7 @@ properties:
- mediatek,mt8173-smi-larb - mediatek,mt8173-smi-larb
- mediatek,mt8183-smi-larb - mediatek,mt8183-smi-larb
- mediatek,mt8192-smi-larb - mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb
- description: for mt7623 - description: for mt7623
items: items:
...@@ -74,6 +75,7 @@ allOf: ...@@ -74,6 +75,7 @@ allOf:
compatible: compatible:
enum: enum:
- mediatek,mt8183-smi-larb - mediatek,mt8183-smi-larb
- mediatek,mt8195-smi-larb
then: then:
properties: properties:
...@@ -108,6 +110,7 @@ allOf: ...@@ -108,6 +110,7 @@ allOf:
- mediatek,mt6779-smi-larb - mediatek,mt6779-smi-larb
- mediatek,mt8167-smi-larb - mediatek,mt8167-smi-larb
- mediatek,mt8192-smi-larb - mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb
then: then:
required: required:
......
...@@ -164,12 +164,20 @@ patternProperties: ...@@ -164,12 +164,20 @@ patternProperties:
"#size-cells": "#size-cells":
const: 0 const: 0
lpddr2:
$ref: "ddr/jedec,lpddr2.yaml#"
type: object
patternProperties: patternProperties:
"^emc-table@[0-9]+$": "^emc-table@[0-9]+$":
$ref: "#/$defs/emc-table" $ref: "#/$defs/emc-table"
required: oneOf:
- nvidia,ram-code - required:
- nvidia,ram-code
- required:
- lpddr2
additionalProperties: false additionalProperties: false
...@@ -227,4 +235,15 @@ examples: ...@@ -227,4 +235,15 @@ examples:
0x00000000 0x00000000 0x00000000 0x00000000>; 0x00000000 0x00000000 0x00000000 0x00000000>;
}; };
}; };
emc-tables@1 {
reg = <1>;
lpddr2 {
compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
revision-id1 = <1>;
density = <2048>;
io-width = <16>;
};
};
}; };
...@@ -33,6 +33,7 @@ properties: ...@@ -33,6 +33,7 @@ properties:
- renesas,r8a77970-rpc-if # R-Car V3M - renesas,r8a77970-rpc-if # R-Car V3M
- renesas,r8a77980-rpc-if # R-Car V3H - renesas,r8a77980-rpc-if # R-Car V3H
- renesas,r8a77995-rpc-if # R-Car D3 - renesas,r8a77995-rpc-if # R-Car D3
- renesas,r8a779a0-rpc-if # R-Car V3U
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device
reg: reg:
......
...@@ -51,7 +51,8 @@ properties: ...@@ -51,7 +51,8 @@ properties:
$ref: '/schemas/types.yaml#/definitions/phandle' $ref: '/schemas/types.yaml#/definitions/phandle'
description: | description: |
phandle of the connected DRAM memory device. For more information please phandle of the connected DRAM memory device. For more information please
refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt refer to documentation file:
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
operating-points-v2: true operating-points-v2: true
......
...@@ -19,6 +19,7 @@ properties: ...@@ -19,6 +19,7 @@ properties:
- qcom,mdm9607-rpmpd - qcom,mdm9607-rpmpd
- qcom,msm8916-rpmpd - qcom,msm8916-rpmpd
- qcom,msm8939-rpmpd - qcom,msm8939-rpmpd
- qcom,msm8953-rpmpd
- qcom,msm8976-rpmpd - qcom,msm8976-rpmpd
- qcom,msm8994-rpmpd - qcom,msm8994-rpmpd
- qcom,msm8996-rpmpd - qcom,msm8996-rpmpd
...@@ -31,6 +32,7 @@ properties: ...@@ -31,6 +32,7 @@ properties:
- qcom,sdm845-rpmhpd - qcom,sdm845-rpmhpd
- qcom,sdx55-rpmhpd - qcom,sdx55-rpmhpd
- qcom,sm6115-rpmpd - qcom,sm6115-rpmpd
- qcom,sm6350-rpmhpd
- qcom,sm8150-rpmhpd - qcom,sm8150-rpmhpd
- qcom,sm8250-rpmhpd - qcom,sm8250-rpmhpd
- qcom,sm8350-rpmhpd - qcom,sm8350-rpmhpd
......
...@@ -20,7 +20,9 @@ properties: ...@@ -20,7 +20,9 @@ properties:
pattern: "^reset-controller@[0-9a-f]+$" pattern: "^reset-controller@[0-9a-f]+$"
compatible: compatible:
const: microchip,sparx5-switch-reset enum:
- microchip,sparx5-switch-reset
- microchip,lan966x-switch-reset
reg: reg:
items: items:
......
...@@ -23,6 +23,7 @@ properties: ...@@ -23,6 +23,7 @@ properties:
- socionext,uniphier-pxs2-usb3-reset - socionext,uniphier-pxs2-usb3-reset
- socionext,uniphier-ld20-usb3-reset - socionext,uniphier-ld20-usb3-reset
- socionext,uniphier-pxs3-usb3-reset - socionext,uniphier-pxs3-usb3-reset
- socionext,uniphier-nx1-usb3-reset
- socionext,uniphier-pro4-ahci-reset - socionext,uniphier-pro4-ahci-reset
- socionext,uniphier-pxs2-ahci-reset - socionext,uniphier-pxs2-ahci-reset
- socionext,uniphier-pxs3-ahci-reset - socionext,uniphier-pxs3-ahci-reset
......
...@@ -23,6 +23,7 @@ properties: ...@@ -23,6 +23,7 @@ properties:
- socionext,uniphier-ld11-reset - socionext,uniphier-ld11-reset
- socionext,uniphier-ld20-reset - socionext,uniphier-ld20-reset
- socionext,uniphier-pxs3-reset - socionext,uniphier-pxs3-reset
- socionext,uniphier-nx1-reset
- description: Media I/O (MIO) reset, SD reset - description: Media I/O (MIO) reset, SD reset
enum: enum:
- socionext,uniphier-ld4-mio-reset - socionext,uniphier-ld4-mio-reset
...@@ -34,6 +35,7 @@ properties: ...@@ -34,6 +35,7 @@ properties:
- socionext,uniphier-ld11-sd-reset - socionext,uniphier-ld11-sd-reset
- socionext,uniphier-ld20-sd-reset - socionext,uniphier-ld20-sd-reset
- socionext,uniphier-pxs3-sd-reset - socionext,uniphier-pxs3-sd-reset
- socionext,uniphier-nx1-sd-reset
- description: Peripheral reset - description: Peripheral reset
enum: enum:
- socionext,uniphier-ld4-peri-reset - socionext,uniphier-ld4-peri-reset
...@@ -44,6 +46,7 @@ properties: ...@@ -44,6 +46,7 @@ properties:
- socionext,uniphier-ld11-peri-reset - socionext,uniphier-ld11-peri-reset
- socionext,uniphier-ld20-peri-reset - socionext,uniphier-ld20-peri-reset
- socionext,uniphier-pxs3-peri-reset - socionext,uniphier-pxs3-peri-reset
- socionext,uniphier-nx1-peri-reset
- description: Analog signal amplifier reset - description: Analog signal amplifier reset
enum: enum:
- socionext,uniphier-ld11-adamv-reset - socionext,uniphier-ld11-adamv-reset
......
...@@ -19,8 +19,7 @@ description: ...@@ -19,8 +19,7 @@ description:
The AOSS side channel exposes control over a set of resources, used to control The AOSS side channel exposes control over a set of resources, used to control
a set of debug related clocks and to affect the low power state of resources a set of debug related clocks and to affect the low power state of resources
related to the secondary subsystems. These resources are exposed as a set of related to the secondary subsystems.
power-domains.
properties: properties:
compatible: compatible:
...@@ -30,6 +29,7 @@ properties: ...@@ -30,6 +29,7 @@ properties:
- qcom,sc7280-aoss-qmp - qcom,sc7280-aoss-qmp
- qcom,sc8180x-aoss-qmp - qcom,sc8180x-aoss-qmp
- qcom,sdm845-aoss-qmp - qcom,sdm845-aoss-qmp
- qcom,sm6350-aoss-qmp
- qcom,sm8150-aoss-qmp - qcom,sm8150-aoss-qmp
- qcom,sm8250-aoss-qmp - qcom,sm8250-aoss-qmp
- qcom,sm8350-aoss-qmp - qcom,sm8350-aoss-qmp
...@@ -57,13 +57,6 @@ properties: ...@@ -57,13 +57,6 @@ properties:
description: description:
The single clock represents the QDSS clock. The single clock represents the QDSS clock.
"#power-domain-cells":
const: 1
description: |
The provided power-domains are:
CDSP state (0), LPASS state (1), modem state (2), SLPI
state (3), SPSS state (4) and Venus state (5).
required: required:
- compatible - compatible
- reg - reg
...@@ -101,7 +94,6 @@ examples: ...@@ -101,7 +94,6 @@ examples:
mboxes = <&apss_shared 0>; mboxes = <&apss_shared 0>;
#clock-cells = <0>; #clock-cells = <0>;
#power-domain-cells = <1>;
cx_cdev: cx { cx_cdev: cx {
#cooling-cells = <2>; #cooling-cells = <2>;
......
...@@ -34,6 +34,7 @@ properties: ...@@ -34,6 +34,7 @@ properties:
- qcom,rpm-ipq6018 - qcom,rpm-ipq6018
- qcom,rpm-msm8226 - qcom,rpm-msm8226
- qcom,rpm-msm8916 - qcom,rpm-msm8916
- qcom,rpm-msm8953
- qcom,rpm-msm8974 - qcom,rpm-msm8974
- qcom,rpm-msm8976 - qcom,rpm-msm8976
- qcom,rpm-msm8996 - qcom,rpm-msm8996
...@@ -41,6 +42,7 @@ properties: ...@@ -41,6 +42,7 @@ properties:
- qcom,rpm-sdm660 - qcom,rpm-sdm660
- qcom,rpm-sm6115 - qcom,rpm-sm6115
- qcom,rpm-sm6125 - qcom,rpm-sm6125
- qcom,rpm-qcm2290
- qcom,rpm-qcs404 - qcom,rpm-qcs404
qcom,smd-channels: qcom,smd-channels:
...@@ -57,6 +59,7 @@ if: ...@@ -57,6 +59,7 @@ if:
- qcom,rpm-apq8084 - qcom,rpm-apq8084
- qcom,rpm-msm8916 - qcom,rpm-msm8916
- qcom,rpm-msm8974 - qcom,rpm-msm8974
- qcom,rpm-msm8953
then: then:
required: required:
- qcom,smd-channels - qcom,smd-channels
......
...@@ -10,14 +10,18 @@ maintainers: ...@@ -10,14 +10,18 @@ maintainers:
- Andy Gross <agross@kernel.org> - Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org> - Bjorn Andersson <bjorn.andersson@linaro.org>
description: | description:
This binding describes the Qualcomm Shared Memory Manager, used to share data This binding describes the Qualcomm Shared Memory Manager, a region of
between various subsystems and OSes in Qualcomm platforms. reserved-memory used to share data between various subsystems and OSes in
Qualcomm platforms.
properties: properties:
compatible: compatible:
const: qcom,smem const: qcom,smem
reg:
maxItems: 1
memory-region: memory-region:
maxItems: 1 maxItems: 1
description: handle to memory reservation for main SMEM memory region. description: handle to memory reservation for main SMEM memory region.
...@@ -29,11 +33,19 @@ properties: ...@@ -29,11 +33,19 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
description: handle to RPM message memory resource description: handle to RPM message memory resource
no-map: true
required: required:
- compatible - compatible
- memory-region
- hwlocks - hwlocks
oneOf:
- required:
- reg
- no-map
- required:
- memory-region
additionalProperties: false additionalProperties: false
examples: examples:
...@@ -43,6 +55,20 @@ examples: ...@@ -43,6 +55,20 @@ examples:
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
smem@fa00000 {
compatible = "qcom,smem";
reg = <0xfa00000 0x200000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
};
- |
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
smem_region: smem@fa00000 { smem_region: smem@fa00000 {
reg = <0xfa00000 0x200000>; reg = <0xfa00000 0x200000>;
no-map; no-map;
......
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Subsystem Power Manager binding
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
This binding describes the Qualcomm Subsystem Power Manager, used to control
the peripheral logic surrounding the application cores in Qualcomm platforms.
properties:
compatible:
items:
- enum:
- qcom,sdm660-gold-saw2-v4.1-l2
- qcom,sdm660-silver-saw2-v4.1-l2
- qcom,msm8998-gold-saw2-v4.1-l2
- qcom,msm8998-silver-saw2-v4.1-l2
- qcom,msm8916-saw2-v3.0-cpu
- qcom,msm8226-saw2-v2.1-cpu
- qcom,msm8974-saw2-v2.1-cpu
- qcom,apq8084-saw2-v2.1-cpu
- qcom,apq8064-saw2-v1.1-cpu
- const: qcom,saw2
reg:
description: Base address and size of the SPM register region
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
/* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "qcom,kryo";
device_type = "cpu";
enable-method = "qcom,kpss-acc-v2";
qcom,saw = <&saw0>;
reg = <0x0>;
operating-points-v2 = <&cpu_opp_table>;
};
};
saw0: power-manager@f9089000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>;
};
- |
/*
* Example 2: New-gen multi cluster SoC using SAW only for L2;
* This does not require any cpuidle driver, nor any cpu phandle.
*/
power-manager@17812000 {
compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2";
reg = <0x17812000 0x1000>;
};
power-manager@17912000 {
compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2";
reg = <0x17912000 0x1000>;
};
...
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) Stats bindings
maintainers:
- Maulik Shah <mkshah@codeaurora.org>
description:
Always On Processor/Resource Power Manager maintains statistics of the SoC
sleep modes involving powering down of the rails and oscillator clock.
Statistics includes SoC sleep mode type, number of times low power mode were
entered, time of last entry, time of last exit and accumulated sleep duration.
properties:
compatible:
enum:
- qcom,rpmh-stats
- qcom,rpm-stats
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
# Example of rpmh sleep stats
- |
sram@c3f0000 {
compatible = "qcom,rpmh-stats";
reg = <0x0c3f0000 0x400>;
};
# Example of rpm sleep stats
- |
sram@4690000 {
compatible = "qcom,rpm-stats";
reg = <0x04690000 0x10000>;
};
...
...@@ -31,6 +31,7 @@ properties: ...@@ -31,6 +31,7 @@ properties:
- amlogic,meson-gxbb-sram - amlogic,meson-gxbb-sram
- arm,juno-sram-ns - arm,juno-sram-ns
- atmel,sama5d2-securam - atmel,sama5d2-securam
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram - rockchip,rk3288-pmu-sram
reg: reg:
...@@ -135,7 +136,9 @@ if: ...@@ -135,7 +136,9 @@ if:
properties: properties:
compatible: compatible:
contains: contains:
const: rockchip,rk3288-pmu-sram enum:
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
else: else:
required: required:
......
...@@ -359,6 +359,8 @@ patternProperties: ...@@ -359,6 +359,8 @@ patternProperties:
description: Shenzhen Elida Technology Co., Ltd. description: Shenzhen Elida Technology Co., Ltd.
"^elimo,.*": "^elimo,.*":
description: Elimo Engineering Ltd. description: Elimo Engineering Ltd.
"^elpida,.*":
description: Elpida Memory, Inc.
"^embest,.*": "^embest,.*":
description: Shenzhen Embest Technology Co., Ltd. description: Shenzhen Embest Technology Co., Ltd.
"^emlid,.*": "^emlid,.*":
......
...@@ -11992,6 +11992,14 @@ M: Sean Wang <sean.wang@mediatek.com> ...@@ -11992,6 +11992,14 @@ M: Sean Wang <sean.wang@mediatek.com>
S: Maintained S: Maintained
F: drivers/char/hw_random/mtk-rng.c F: drivers/char/hw_random/mtk-rng.c
MEDIATEK SMI DRIVER
M: Yong Wu <yong.wu@mediatek.com>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/memory-controllers/mediatek,smi*
F: drivers/memory/mtk-smi.c
F: include/soc/mediatek/smi.h
MEDIATEK SWITCH DRIVER MEDIATEK SWITCH DRIVER
M: Sean Wang <sean.wang@mediatek.com> M: Sean Wang <sean.wang@mediatek.com>
M: Landen Chao <Landen.Chao@mediatek.com> M: Landen Chao <Landen.Chao@mediatek.com>
......
...@@ -351,7 +351,7 @@ config ARCH_EP93XX ...@@ -351,7 +351,7 @@ config ARCH_EP93XX
select CLKSRC_MMIO select CLKSRC_MMIO
select CPU_ARM920T select CPU_ARM920T
select GPIOLIB select GPIOLIB
select HAVE_LEGACY_CLK select COMMON_CLK
help help
This enables support for the Cirrus EP93xx series of CPUs. This enables support for the Cirrus EP93xx series of CPUs.
...@@ -480,7 +480,6 @@ config ARCH_S3C24XX ...@@ -480,7 +480,6 @@ config ARCH_S3C24XX
select GPIOLIB select GPIOLIB
select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_MULTI_HANDLER
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_IO_H select NEED_MACH_IO_H
select S3C2410_WATCHDOG select S3C2410_WATCHDOG
select SAMSUNG_ATAGS select SAMSUNG_ATAGS
......
This diff is collapsed.
...@@ -214,7 +214,7 @@ static int ep93xx_ohci_power_on(struct platform_device *pdev) ...@@ -214,7 +214,7 @@ static int ep93xx_ohci_power_on(struct platform_device *pdev)
return PTR_ERR(ep93xx_ohci_host_clock); return PTR_ERR(ep93xx_ohci_host_clock);
} }
return clk_enable(ep93xx_ohci_host_clock); return clk_prepare_enable(ep93xx_ohci_host_clock);
} }
static void ep93xx_ohci_power_off(struct platform_device *pdev) static void ep93xx_ohci_power_off(struct platform_device *pdev)
......
...@@ -111,19 +111,19 @@ ...@@ -111,19 +111,19 @@
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) #define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) #define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28) #define EP93XX_SYSCON_PWRCNT_USH_EN 28
#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27) #define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26) #define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25) #define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24) #define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23) #define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22) #define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21) #define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20) #define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19) #define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18) #define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17) #define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16) #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
...@@ -139,13 +139,13 @@ ...@@ -139,13 +139,13 @@
#define EP93XX_SYSCON_DEVCFG_GONK (1<<27) #define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
#define EP93XX_SYSCON_DEVCFG_TONG (1<<26) #define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
#define EP93XX_SYSCON_DEVCFG_MONG (1<<25) #define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24) #define EP93XX_SYSCON_DEVCFG_U3EN 24
#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) #define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) #define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) #define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20) #define EP93XX_SYSCON_DEVCFG_U2EN 20
#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) #define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18) #define EP93XX_SYSCON_DEVCFG_U1EN 18
#define EP93XX_SYSCON_DEVCFG_TIN (1<<17) #define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) #define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) #define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
...@@ -163,12 +163,12 @@ ...@@ -163,12 +163,12 @@
#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) #define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84) #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15) #define EP93XX_SYSCON_CLKDIV_ENABLE 15
#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) #define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) #define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c) #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31) #define EP93XX_SYSCON_I2SCLKDIV_SENA 31
#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29) #define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19) #define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
#define EP93XX_I2SCLKDIV_SDIV (1 << 16) #define EP93XX_I2SCLKDIV_SDIV (1 << 16)
...@@ -177,9 +177,9 @@ ...@@ -177,9 +177,9 @@
#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31) #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16) #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15) #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c) #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
......
...@@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS ...@@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS
select ARM_GIC select ARM_GIC
select EXYNOS_IRQ_COMBINER select EXYNOS_IRQ_COMBINER
select COMMON_CLK_SAMSUNG select COMMON_CLK_SAMSUNG
select EXYNOS_CHIPID
select EXYNOS_THERMAL select EXYNOS_THERMAL
select EXYNOS_PMU select EXYNOS_PMU
select EXYNOS_SROM select EXYNOS_SROM
...@@ -22,7 +21,6 @@ menuconfig ARCH_EXYNOS ...@@ -22,7 +21,6 @@ menuconfig ARCH_EXYNOS
select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP select HAVE_ARM_SCU if SMP
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM select PM_GENERIC_DOMAINS if PM
......
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#define COREPOR_RST BIT(5) #define COREPOR_RST BIT(5)
#define CORE_RST BIT(4) #define CORE_RST BIT(4)
#define L2DT_SLP BIT(3) #define L2DT_SLP BIT(3)
#define CORE_MEM_CLAMP BIT(1)
#define CLAMP BIT(0) #define CLAMP BIT(0)
#define APC_PWR_GATE_CTL 0x14 #define APC_PWR_GATE_CTL 0x14
...@@ -75,6 +76,62 @@ static int scss_release_secondary(unsigned int cpu) ...@@ -75,6 +76,62 @@ static int scss_release_secondary(unsigned int cpu)
return 0; return 0;
} }
static int cortex_a7_release_secondary(unsigned int cpu)
{
int ret = 0;
void __iomem *reg;
struct device_node *cpu_node, *acc_node;
u32 reg_val;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
if (!acc_node) {
ret = -ENODEV;
goto out_acc;
}
reg = of_iomap(acc_node, 0);
if (!reg) {
ret = -ENOMEM;
goto out_acc_map;
}
/* Put the CPU into reset. */
reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
writel(reg_val, reg + APCS_CPU_PWR_CTL);
/* Turn on the BHS and set the BHS_CNT to 16 XO clock cycles */
writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL);
/* Wait for the BHS to settle */
udelay(2);
reg_val &= ~CORE_MEM_CLAMP;
writel(reg_val, reg + APCS_CPU_PWR_CTL);
reg_val |= L2DT_SLP;
writel(reg_val, reg + APCS_CPU_PWR_CTL);
udelay(2);
reg_val = (reg_val | BIT(17)) & ~CLAMP;
writel(reg_val, reg + APCS_CPU_PWR_CTL);
udelay(2);
/* Release CPU out of reset and bring it to life. */
reg_val &= ~(CORE_RST | COREPOR_RST);
writel(reg_val, reg + APCS_CPU_PWR_CTL);
reg_val |= CORE_PWRD_UP;
writel(reg_val, reg + APCS_CPU_PWR_CTL);
iounmap(reg);
out_acc_map:
of_node_put(acc_node);
out_acc:
of_node_put(cpu_node);
return ret;
}
static int kpssv1_release_secondary(unsigned int cpu) static int kpssv1_release_secondary(unsigned int cpu)
{ {
int ret = 0; int ret = 0;
...@@ -281,6 +338,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -281,6 +338,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
return qcom_boot_secondary(cpu, scss_release_secondary); return qcom_boot_secondary(cpu, scss_release_secondary);
} }
static int cortex_a7_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
return qcom_boot_secondary(cpu, cortex_a7_release_secondary);
}
static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle) static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
{ {
return qcom_boot_secondary(cpu, kpssv1_release_secondary); return qcom_boot_secondary(cpu, kpssv1_release_secondary);
...@@ -315,6 +377,16 @@ static const struct smp_operations smp_msm8660_ops __initconst = { ...@@ -315,6 +377,16 @@ static const struct smp_operations smp_msm8660_ops __initconst = {
}; };
CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops); CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
static const struct smp_operations qcom_smp_cortex_a7_ops __initconst = {
.smp_prepare_cpus = qcom_smp_prepare_cpus,
.smp_boot_secondary = cortex_a7_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = qcom_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(qcom_smp_msm8226, "qcom,msm8226-smp", &qcom_smp_cortex_a7_ops);
CPU_METHOD_OF_DECLARE(qcom_smp_msm8916, "qcom,msm8916-smp", &qcom_smp_cortex_a7_ops);
static const struct smp_operations qcom_smp_kpssv1_ops __initconst = { static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
.smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_prepare_cpus = qcom_smp_prepare_cpus,
.smp_boot_secondary = kpssv1_boot_secondary, .smp_boot_secondary = kpssv1_boot_secondary,
......
...@@ -13,7 +13,6 @@ config ARCH_S5PV210 ...@@ -13,7 +13,6 @@ config ARCH_S5PV210
select COMMON_CLK_SAMSUNG select COMMON_CLK_SAMSUNG
select GPIOLIB select GPIOLIB
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select SOC_SAMSUNG select SOC_SAMSUNG
......
...@@ -89,10 +89,8 @@ config ARCH_BRCMSTB ...@@ -89,10 +89,8 @@ config ARCH_BRCMSTB
config ARCH_EXYNOS config ARCH_EXYNOS
bool "ARMv8 based Samsung Exynos SoC family" bool "ARMv8 based Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG select COMMON_CLK_SAMSUNG
select EXYNOS_CHIPID
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select EXYNOS_PMU select EXYNOS_PMU
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM select PM_GENERIC_DOMAINS if PM
......
...@@ -30,7 +30,7 @@ config ARM_INTEGRATOR_LM ...@@ -30,7 +30,7 @@ config ARM_INTEGRATOR_LM
found on the ARM Integrator AP (Application Platform) found on the ARM Integrator AP (Application Platform)
config BRCMSTB_GISB_ARB config BRCMSTB_GISB_ARB
bool "Broadcom STB GISB bus arbiter" tristate "Broadcom STB GISB bus arbiter"
depends on ARM || ARM64 || MIPS depends on ARM || ARM64 || MIPS
default ARCH_BRCMSTB || BMIPS_GENERIC default ARCH_BRCMSTB || BMIPS_GENERIC
help help
......
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (C) 2014-2017 Broadcom * Copyright (C) 2014-2021 Broadcom
*/ */
#include <linux/init.h> #include <linux/init.h>
...@@ -536,6 +536,7 @@ static struct platform_driver brcmstb_gisb_arb_driver = { ...@@ -536,6 +536,7 @@ static struct platform_driver brcmstb_gisb_arb_driver = {
.name = "brcm-gisb-arb", .name = "brcm-gisb-arb",
.of_match_table = brcmstb_gisb_arb_of_match, .of_match_table = brcmstb_gisb_arb_of_match,
.pm = &brcmstb_gisb_arb_pm_ops, .pm = &brcmstb_gisb_arb_pm_ops,
.suppress_bind_attrs = true,
}, },
}; };
...@@ -546,3 +547,7 @@ static int __init brcm_gisb_driver_init(void) ...@@ -546,3 +547,7 @@ static int __init brcm_gisb_driver_init(void)
} }
module_init(brcm_gisb_driver_init); module_init(brcm_gisb_driver_init);
MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Broadcom STB GISB arbiter driver");
MODULE_LICENSE("GPL v2");
...@@ -15,10 +15,9 @@ static int sun50i_de2_bus_probe(struct platform_device *pdev) ...@@ -15,10 +15,9 @@ static int sun50i_de2_bus_probe(struct platform_device *pdev)
int ret; int ret;
ret = sunxi_sram_claim(&pdev->dev); ret = sunxi_sram_claim(&pdev->dev);
if (ret) { if (ret)
dev_err(&pdev->dev, "Error couldn't map SRAM to device\n"); return dev_err_probe(&pdev->dev, ret,
return ret; "Couldn't map SRAM to device\n");
}
of_platform_populate(np, NULL, NULL, &pdev->dev); of_platform_populate(np, NULL, NULL, &pdev->dev);
......
This diff is collapsed.
...@@ -99,7 +99,7 @@ config ARM_MVEBU_V7_CPUIDLE ...@@ -99,7 +99,7 @@ config ARM_MVEBU_V7_CPUIDLE
config ARM_TEGRA_CPUIDLE config ARM_TEGRA_CPUIDLE
bool "CPU Idle Driver for NVIDIA Tegra SoCs" bool "CPU Idle Driver for NVIDIA Tegra SoCs"
depends on ARCH_TEGRA && !ARM64 depends on (ARCH_TEGRA || COMPILE_TEST) && !ARM64 && MMU
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_CPU_SUSPEND select ARM_CPU_SUSPEND
help help
...@@ -112,6 +112,7 @@ config ARM_QCOM_SPM_CPUIDLE ...@@ -112,6 +112,7 @@ config ARM_QCOM_SPM_CPUIDLE
select CPU_IDLE_MULTIPLE_DRIVERS select CPU_IDLE_MULTIPLE_DRIVERS
select DT_IDLE_STATES select DT_IDLE_STATES
select QCOM_SCM select QCOM_SCM
select QCOM_SPM
help help
Select this to enable cpuidle for Qualcomm processors. Select this to enable cpuidle for Qualcomm processors.
The Subsystem Power Manager (SPM) controls low power modes for the The Subsystem Power Manager (SPM) controls low power modes for the
......
This diff is collapsed.
...@@ -337,6 +337,9 @@ static void tegra_cpuidle_setup_tegra114_c7_state(void) ...@@ -337,6 +337,9 @@ static void tegra_cpuidle_setup_tegra114_c7_state(void)
static int tegra_cpuidle_probe(struct platform_device *pdev) static int tegra_cpuidle_probe(struct platform_device *pdev)
{ {
if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NOT_READY)
return -EPROBE_DEFER;
/* LP2 could be disabled in device-tree */ /* LP2 could be disabled in device-tree */
if (tegra_pmc_get_suspend_mode() < TEGRA_SUSPEND_LP2) if (tegra_pmc_get_suspend_mode() < TEGRA_SUSPEND_LP2)
tegra_cpuidle_disable_state(TEGRA_CC6); tegra_cpuidle_disable_state(TEGRA_CC6);
......
...@@ -167,6 +167,27 @@ struct ffa_drv_info { ...@@ -167,6 +167,27 @@ struct ffa_drv_info {
static struct ffa_drv_info *drv_info; static struct ffa_drv_info *drv_info;
/*
* The driver must be able to support all the versions from the earliest
* supported FFA_MIN_VERSION to the latest supported FFA_DRIVER_VERSION.
* The specification states that if firmware supports a FFA implementation
* that is incompatible with and at a greater version number than specified
* by the caller(FFA_DRIVER_VERSION passed as parameter to FFA_VERSION),
* it must return the NOT_SUPPORTED error code.
*/
static u32 ffa_compatible_version_find(u32 version)
{
u16 major = MAJOR_VERSION(version), minor = MINOR_VERSION(version);
u16 drv_major = MAJOR_VERSION(FFA_DRIVER_VERSION);
u16 drv_minor = MINOR_VERSION(FFA_DRIVER_VERSION);
if ((major < drv_major) || (major == drv_major && minor <= drv_minor))
return version;
pr_info("Firmware version higher than driver version, downgrading\n");
return FFA_DRIVER_VERSION;
}
static int ffa_version_check(u32 *version) static int ffa_version_check(u32 *version)
{ {
ffa_value_t ver; ffa_value_t ver;
...@@ -180,15 +201,20 @@ static int ffa_version_check(u32 *version) ...@@ -180,15 +201,20 @@ static int ffa_version_check(u32 *version)
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
if (ver.a0 < FFA_MIN_VERSION || ver.a0 > FFA_DRIVER_VERSION) { if (ver.a0 < FFA_MIN_VERSION) {
pr_err("Incompatible version %d.%d found\n", pr_err("Incompatible v%d.%d! Earliest supported v%d.%d\n",
MAJOR_VERSION(ver.a0), MINOR_VERSION(ver.a0)); MAJOR_VERSION(ver.a0), MINOR_VERSION(ver.a0),
MAJOR_VERSION(FFA_MIN_VERSION),
MINOR_VERSION(FFA_MIN_VERSION));
return -EINVAL; return -EINVAL;
} }
*version = ver.a0; pr_info("Driver version %d.%d\n", MAJOR_VERSION(FFA_DRIVER_VERSION),
pr_info("Version %d.%d found\n", MAJOR_VERSION(ver.a0), MINOR_VERSION(FFA_DRIVER_VERSION));
pr_info("Firmware version %d.%d found\n", MAJOR_VERSION(ver.a0),
MINOR_VERSION(ver.a0)); MINOR_VERSION(ver.a0));
*version = ffa_compatible_version_find(ver.a0);
return 0; return 0;
} }
...@@ -586,6 +612,22 @@ ffa_memory_share(struct ffa_device *dev, struct ffa_mem_ops_args *args) ...@@ -586,6 +612,22 @@ ffa_memory_share(struct ffa_device *dev, struct ffa_mem_ops_args *args)
return ffa_memory_ops(FFA_FN_NATIVE(MEM_SHARE), args); return ffa_memory_ops(FFA_FN_NATIVE(MEM_SHARE), args);
} }
static int
ffa_memory_lend(struct ffa_device *dev, struct ffa_mem_ops_args *args)
{
/* Note that upon a successful MEM_LEND request the caller
* must ensure that the memory region specified is not accessed
* until a successful MEM_RECALIM call has been made.
* On systems with a hypervisor present this will been enforced,
* however on systems without a hypervisor the responsibility
* falls to the calling kernel driver to prevent access.
*/
if (dev->mode_32bit)
return ffa_memory_ops(FFA_MEM_LEND, args);
return ffa_memory_ops(FFA_FN_NATIVE(MEM_LEND), args);
}
static const struct ffa_dev_ops ffa_ops = { static const struct ffa_dev_ops ffa_ops = {
.api_version_get = ffa_api_version_get, .api_version_get = ffa_api_version_get,
.partition_info_get = ffa_partition_info_get, .partition_info_get = ffa_partition_info_get,
...@@ -593,6 +635,7 @@ static const struct ffa_dev_ops ffa_ops = { ...@@ -593,6 +635,7 @@ static const struct ffa_dev_ops ffa_ops = {
.sync_send_receive = ffa_sync_send_receive, .sync_send_receive = ffa_sync_send_receive,
.memory_reclaim = ffa_memory_reclaim, .memory_reclaim = ffa_memory_reclaim,
.memory_share = ffa_memory_share, .memory_share = ffa_memory_share,
.memory_lend = ffa_memory_lend,
}; };
const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev)
......
...@@ -252,7 +252,7 @@ static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, ...@@ -252,7 +252,7 @@ static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
break; break;
default: default:
pr_err("Unknown SMC convention being used\n"); pr_err("Unknown SMC convention being used\n");
return -EINVAL; return false;
} }
ret = qcom_scm_call(dev, &desc, &res); ret = qcom_scm_call(dev, &desc, &res);
...@@ -1348,6 +1348,10 @@ static const struct of_device_id qcom_scm_dt_match[] = { ...@@ -1348,6 +1348,10 @@ static const struct of_device_id qcom_scm_dt_match[] = {
SCM_HAS_IFACE_CLK | SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK) SCM_HAS_BUS_CLK)
}, },
{ .compatible = "qcom,scm-msm8953", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK | { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
SCM_HAS_IFACE_CLK | SCM_HAS_IFACE_CLK |
SCM_HAS_BUS_CLK) SCM_HAS_BUS_CLK)
......
...@@ -74,28 +74,36 @@ static void seqbuf_seek(struct seqbuf *seqbuf, ssize_t offset) ...@@ -74,28 +74,36 @@ static void seqbuf_seek(struct seqbuf *seqbuf, ssize_t offset)
static const char *get_filename(struct tegra_bpmp *bpmp, static const char *get_filename(struct tegra_bpmp *bpmp,
const struct file *file, char *buf, int size) const struct file *file, char *buf, int size)
{ {
char root_path_buf[512]; const char *root_path, *filename = NULL;
const char *root_path; char *root_path_buf;
const char *filename;
size_t root_len; size_t root_len;
root_path_buf = kzalloc(512, GFP_KERNEL);
if (!root_path_buf)
goto out;
root_path = dentry_path(bpmp->debugfs_mirror, root_path_buf, root_path = dentry_path(bpmp->debugfs_mirror, root_path_buf,
sizeof(root_path_buf)); sizeof(root_path_buf));
if (IS_ERR(root_path)) if (IS_ERR(root_path))
return NULL; goto out;
root_len = strlen(root_path); root_len = strlen(root_path);
filename = dentry_path(file->f_path.dentry, buf, size); filename = dentry_path(file->f_path.dentry, buf, size);
if (IS_ERR(filename)) if (IS_ERR(filename)) {
return NULL; filename = NULL;
goto out;
}
if (strlen(filename) < root_len || if (strlen(filename) < root_len || strncmp(filename, root_path, root_len)) {
strncmp(filename, root_path, root_len)) filename = NULL;
return NULL; goto out;
}
filename += root_len; filename += root_len;
out:
kfree(root_path_buf);
return filename; return filename;
} }
......
...@@ -162,7 +162,6 @@ static int tegra210_bpmp_init(struct tegra_bpmp *bpmp) ...@@ -162,7 +162,6 @@ static int tegra210_bpmp_init(struct tegra_bpmp *bpmp)
{ {
struct platform_device *pdev = to_platform_device(bpmp->dev); struct platform_device *pdev = to_platform_device(bpmp->dev);
struct tegra210_bpmp *priv; struct tegra210_bpmp *priv;
struct resource *res;
unsigned int i; unsigned int i;
int err; int err;
...@@ -172,13 +171,11 @@ static int tegra210_bpmp_init(struct tegra_bpmp *bpmp) ...@@ -172,13 +171,11 @@ static int tegra210_bpmp_init(struct tegra_bpmp *bpmp)
bpmp->priv = priv; bpmp->priv = priv;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->atomics = devm_platform_ioremap_resource(pdev, 0);
priv->atomics = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->atomics)) if (IS_ERR(priv->atomics))
return PTR_ERR(priv->atomics); return PTR_ERR(priv->atomics);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); priv->arb_sema = devm_platform_ioremap_resource(pdev, 1);
priv->arb_sema = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->arb_sema)) if (IS_ERR(priv->arb_sema))
return PTR_ERR(priv->arb_sema); return PTR_ERR(priv->arb_sema);
......
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/phy/phy.h> #include <linux/phy/phy.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/reset.h>
#include <video/mipi_display.h> #include <video/mipi_display.h>
#include <video/videomode.h> #include <video/videomode.h>
...@@ -980,8 +981,10 @@ static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) ...@@ -980,8 +981,10 @@ static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
struct mtk_dsi *dsi = dev_get_drvdata(dev); struct mtk_dsi *dsi = dev_get_drvdata(dev);
ret = mtk_dsi_encoder_init(drm, dsi); ret = mtk_dsi_encoder_init(drm, dsi);
if (ret)
return ret;
return ret; return device_reset_optional(dev);
} }
static void mtk_dsi_unbind(struct device *dev, struct device *master, static void mtk_dsi_unbind(struct device *dev, struct device *master,
......
...@@ -55,8 +55,8 @@ config ATMEL_EBI ...@@ -55,8 +55,8 @@ config ATMEL_EBI
SRAMs, ATA devices, etc. SRAMs, ATA devices, etc.
config BRCMSTB_DPFE config BRCMSTB_DPFE
bool "Broadcom STB DPFE driver" if COMPILE_TEST tristate "Broadcom STB DPFE driver"
default y if ARCH_BRCMSTB default ARCH_BRCMSTB
depends on ARCH_BRCMSTB || COMPILE_TEST depends on ARCH_BRCMSTB || COMPILE_TEST
help help
This driver provides access to the DPFE interface of Broadcom This driver provides access to the DPFE interface of Broadcom
...@@ -210,6 +210,7 @@ config RENESAS_RPCIF ...@@ -210,6 +210,7 @@ config RENESAS_RPCIF
tristate "Renesas RPC-IF driver" tristate "Renesas RPC-IF driver"
depends on ARCH_RENESAS || COMPILE_TEST depends on ARCH_RENESAS || COMPILE_TEST
select REGMAP_MMIO select REGMAP_MMIO
select RESET_CONTROLLER
help help
This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
either SPI host or HyperFlash. You'll have to select individual either SPI host or HyperFlash. You'll have to select individual
......
...@@ -263,7 +263,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev) ...@@ -263,7 +263,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev); ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
if (ret < 0) if (ret < 0)
goto err; goto err_unmap_nandirq;
init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait); init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
...@@ -272,7 +272,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev) ...@@ -272,7 +272,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
if (ret != 0) { if (ret != 0) {
dev_err(&dev->dev, "failed to install irq (%d)\n", dev_err(&dev->dev, "failed to install irq (%d)\n",
fsl_ifc_ctrl_dev->irq); fsl_ifc_ctrl_dev->irq);
goto err_irq; goto err_unmap_nandirq;
} }
if (fsl_ifc_ctrl_dev->nand_irq) { if (fsl_ifc_ctrl_dev->nand_irq) {
...@@ -281,17 +281,16 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev) ...@@ -281,17 +281,16 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
if (ret != 0) { if (ret != 0) {
dev_err(&dev->dev, "failed to install irq (%d)\n", dev_err(&dev->dev, "failed to install irq (%d)\n",
fsl_ifc_ctrl_dev->nand_irq); fsl_ifc_ctrl_dev->nand_irq);
goto err_nandirq; goto err_free_irq;
} }
} }
return 0; return 0;
err_nandirq: err_free_irq:
free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
err_irq:
free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev); free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
err_unmap_nandirq:
irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
irq_dispose_mapping(fsl_ifc_ctrl_dev->irq); irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
err: err:
iounmap(fsl_ifc_ctrl_dev->gregs); iounmap(fsl_ifc_ctrl_dev->gregs);
......
...@@ -112,6 +112,26 @@ ...@@ -112,6 +112,26 @@
#define NUM_DDR_ADDR_TABLE_ENTRIES 11 #define NUM_DDR_ADDR_TABLE_ENTRIES 11
#define NUM_DDR_TIMING_TABLE_ENTRIES 4 #define NUM_DDR_TIMING_TABLE_ENTRIES 4
#define LPDDR2_MANID_SAMSUNG 1
#define LPDDR2_MANID_QIMONDA 2
#define LPDDR2_MANID_ELPIDA 3
#define LPDDR2_MANID_ETRON 4
#define LPDDR2_MANID_NANYA 5
#define LPDDR2_MANID_HYNIX 6
#define LPDDR2_MANID_MOSEL 7
#define LPDDR2_MANID_WINBOND 8
#define LPDDR2_MANID_ESMT 9
#define LPDDR2_MANID_SPANSION 11
#define LPDDR2_MANID_SST 12
#define LPDDR2_MANID_ZMOS 13
#define LPDDR2_MANID_INTEL 14
#define LPDDR2_MANID_NUMONYX 254
#define LPDDR2_MANID_MICRON 255
#define LPDDR2_TYPE_S4 0
#define LPDDR2_TYPE_S2 1
#define LPDDR2_TYPE_NVM 2
/* Structure for DDR addressing info from the JEDEC spec */ /* Structure for DDR addressing info from the JEDEC spec */
struct lpddr2_addressing { struct lpddr2_addressing {
u32 num_banks; u32 num_banks;
...@@ -170,6 +190,33 @@ extern const struct lpddr2_timings ...@@ -170,6 +190,33 @@ extern const struct lpddr2_timings
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
/* Structure of MR8 */
union lpddr2_basic_config4 {
u32 value;
struct {
unsigned int arch_type : 2;
unsigned int density : 4;
unsigned int io_width : 2;
} __packed;
};
/*
* Structure for information about LPDDR2 chip. All parameters are
* matching raw values of standard mode register bitfields or set to
* -ENOENT if info unavailable.
*/
struct lpddr2_info {
int arch_type;
int density;
int io_width;
int manufacturer_id;
int revision_id1;
int revision_id2;
};
const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id);
/* /*
* Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
* All parameters are in pico seconds(ps) excluding max_freq, min_freq which * All parameters are in pico seconds(ps) excluding max_freq, min_freq which
......
...@@ -131,3 +131,44 @@ const struct lpddr2_min_tck lpddr2_jedec_min_tck = { ...@@ -131,3 +131,44 @@ const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
.tFAW = 8 .tFAW = 8
}; };
EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck); EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id)
{
switch (manufacturer_id) {
case LPDDR2_MANID_SAMSUNG:
return "Samsung";
case LPDDR2_MANID_QIMONDA:
return "Qimonda";
case LPDDR2_MANID_ELPIDA:
return "Elpida";
case LPDDR2_MANID_ETRON:
return "Etron";
case LPDDR2_MANID_NANYA:
return "Nanya";
case LPDDR2_MANID_HYNIX:
return "Hynix";
case LPDDR2_MANID_MOSEL:
return "Mosel";
case LPDDR2_MANID_WINBOND:
return "Winbond";
case LPDDR2_MANID_ESMT:
return "ESMT";
case LPDDR2_MANID_SPANSION:
return "Spansion";
case LPDDR2_MANID_SST:
return "SST";
case LPDDR2_MANID_ZMOS:
return "ZMOS";
case LPDDR2_MANID_INTEL:
return "Intel";
case LPDDR2_MANID_NUMONYX:
return "Numonyx";
case LPDDR2_MANID_MICRON:
return "Micron";
default:
break;
}
return "invalid";
}
EXPORT_SYMBOL_GPL(lpddr2_jedec_manufacturer);
This diff is collapsed.
...@@ -298,3 +298,90 @@ const struct lpddr3_timings ...@@ -298,3 +298,90 @@ const struct lpddr3_timings
return NULL; return NULL;
} }
EXPORT_SYMBOL(of_lpddr3_get_ddr_timings); EXPORT_SYMBOL(of_lpddr3_get_ddr_timings);
/**
* of_lpddr2_get_info() - extracts information about the lpddr2 chip.
* @np: Pointer to device tree node containing lpddr2 info
* @dev: Device requesting info
*
* Populates lpddr2_info structure by extracting data from device
* tree node. Returns pointer to populated structure. If error
* happened while populating, returns NULL. If property is missing
* in a device-tree, then the corresponding value is set to -ENOENT.
*/
const struct lpddr2_info
*of_lpddr2_get_info(struct device_node *np, struct device *dev)
{
struct lpddr2_info *ret_info, info = {};
struct property *prop;
const char *cp;
int err;
err = of_property_read_u32(np, "revision-id1", &info.revision_id1);
if (err)
info.revision_id1 = -ENOENT;
err = of_property_read_u32(np, "revision-id2", &info.revision_id2);
if (err)
info.revision_id2 = -ENOENT;
err = of_property_read_u32(np, "io-width", &info.io_width);
if (err)
return NULL;
info.io_width = 32 / info.io_width - 1;
err = of_property_read_u32(np, "density", &info.density);
if (err)
return NULL;
info.density = ffs(info.density) - 7;
if (of_device_is_compatible(np, "jedec,lpddr2-s4"))
info.arch_type = LPDDR2_TYPE_S4;
else if (of_device_is_compatible(np, "jedec,lpddr2-s2"))
info.arch_type = LPDDR2_TYPE_S2;
else if (of_device_is_compatible(np, "jedec,lpddr2-nvm"))
info.arch_type = LPDDR2_TYPE_NVM;
else
return NULL;
prop = of_find_property(np, "compatible", NULL);
for (cp = of_prop_next_string(prop, NULL); cp;
cp = of_prop_next_string(prop, cp)) {
#define OF_LPDDR2_VENDOR_CMP(compat, ID) \
if (!of_compat_cmp(cp, compat ",", strlen(compat ","))) { \
info.manufacturer_id = LPDDR2_MANID_##ID; \
break; \
}
OF_LPDDR2_VENDOR_CMP("samsung", SAMSUNG)
OF_LPDDR2_VENDOR_CMP("qimonda", QIMONDA)
OF_LPDDR2_VENDOR_CMP("elpida", ELPIDA)
OF_LPDDR2_VENDOR_CMP("etron", ETRON)
OF_LPDDR2_VENDOR_CMP("nanya", NANYA)
OF_LPDDR2_VENDOR_CMP("hynix", HYNIX)
OF_LPDDR2_VENDOR_CMP("mosel", MOSEL)
OF_LPDDR2_VENDOR_CMP("winbond", WINBOND)
OF_LPDDR2_VENDOR_CMP("esmt", ESMT)
OF_LPDDR2_VENDOR_CMP("spansion", SPANSION)
OF_LPDDR2_VENDOR_CMP("sst", SST)
OF_LPDDR2_VENDOR_CMP("zmos", ZMOS)
OF_LPDDR2_VENDOR_CMP("intel", INTEL)
OF_LPDDR2_VENDOR_CMP("numonyx", NUMONYX)
OF_LPDDR2_VENDOR_CMP("micron", MICRON)
#undef OF_LPDDR2_VENDOR_CMP
}
if (!info.manufacturer_id)
info.manufacturer_id = -ENOENT;
ret_info = devm_kzalloc(dev, sizeof(*ret_info), GFP_KERNEL);
if (ret_info)
*ret_info = info;
return ret_info;
}
EXPORT_SYMBOL(of_lpddr2_get_info);
...@@ -20,6 +20,9 @@ const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np, ...@@ -20,6 +20,9 @@ const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,
const struct lpddr3_timings * const struct lpddr3_timings *
of_lpddr3_get_ddr_timings(struct device_node *np_ddr, of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
struct device *dev, u32 device_type, u32 *nr_frequencies); struct device *dev, u32 device_type, u32 *nr_frequencies);
const struct lpddr2_info *of_lpddr2_get_info(struct device_node *np,
struct device *dev);
#else #else
static inline const struct lpddr2_min_tck static inline const struct lpddr2_min_tck
*of_get_min_tck(struct device_node *np, struct device *dev) *of_get_min_tck(struct device_node *np, struct device *dev)
...@@ -46,6 +49,12 @@ static inline const struct lpddr3_timings ...@@ -46,6 +49,12 @@ static inline const struct lpddr3_timings
{ {
return NULL; return NULL;
} }
static inline const struct lpddr2_info
*of_lpddr2_get_info(struct device_node *np, struct device *dev)
{
return NULL;
}
#endif /* CONFIG_OF && CONFIG_DDR */ #endif /* CONFIG_OF && CONFIG_DDR */
#endif /* __LINUX_MEMORY_OF_REG_ */ #endif /* __LINUX_MEMORY_OF_REG_ */
...@@ -160,10 +160,61 @@ static const struct regmap_access_table rpcif_volatile_table = { ...@@ -160,10 +160,61 @@ static const struct regmap_access_table rpcif_volatile_table = {
.n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
}; };
/*
* Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
* with proper width. Requires SMENR_SPIDE to be correctly set before!
*/
static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct rpcif *rpc = context;
if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
if (spide == 0x8) {
*val = readb(rpc->base + reg);
return 0;
} else if (spide == 0xC) {
*val = readw(rpc->base + reg);
return 0;
} else if (spide != 0xF) {
return -EILSEQ;
}
}
*val = readl(rpc->base + reg);
return 0;
}
static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct rpcif *rpc = context;
if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
if (spide == 0x8) {
writeb(val, rpc->base + reg);
return 0;
} else if (spide == 0xC) {
writew(val, rpc->base + reg);
return 0;
} else if (spide != 0xF) {
return -EILSEQ;
}
}
writel(val, rpc->base + reg);
return 0;
}
static const struct regmap_config rpcif_regmap_config = { static const struct regmap_config rpcif_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.val_bits = 32, .val_bits = 32,
.reg_stride = 4, .reg_stride = 4,
.reg_read = rpcif_reg_read,
.reg_write = rpcif_reg_write,
.fast_io = true, .fast_io = true,
.max_register = RPCIF_PHYINT, .max_register = RPCIF_PHYINT,
.volatile_table = &rpcif_volatile_table, .volatile_table = &rpcif_volatile_table,
...@@ -173,17 +224,15 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev) ...@@ -173,17 +224,15 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
{ {
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
struct resource *res; struct resource *res;
void __iomem *base;
rpc->dev = dev; rpc->dev = dev;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
base = devm_ioremap_resource(&pdev->dev, res); rpc->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base)) if (IS_ERR(rpc->base))
return PTR_ERR(base); return PTR_ERR(rpc->base);
rpc->regmap = devm_regmap_init_mmio(&pdev->dev, base, rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
&rpcif_regmap_config);
if (IS_ERR(rpc->regmap)) { if (IS_ERR(rpc->regmap)) {
dev_err(&pdev->dev, dev_err(&pdev->dev,
"failed to init regmap for rpcif, error %ld\n", "failed to init regmap for rpcif, error %ld\n",
...@@ -354,20 +403,16 @@ void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, ...@@ -354,20 +403,16 @@ void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
nbytes = op->data.nbytes; nbytes = op->data.nbytes;
rpc->xferlen = nbytes; rpc->xferlen = nbytes;
rpc->enable |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)) | rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
} }
} }
EXPORT_SYMBOL(rpcif_prepare); EXPORT_SYMBOL(rpcif_prepare);
int rpcif_manual_xfer(struct rpcif *rpc) int rpcif_manual_xfer(struct rpcif *rpc)
{ {
u32 smenr, smcr, pos = 0, max = 4; u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
int ret = 0; int ret = 0;
if (rpc->bus_size == 2)
max = 8;
pm_runtime_get_sync(rpc->dev); pm_runtime_get_sync(rpc->dev);
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
...@@ -378,37 +423,36 @@ int rpcif_manual_xfer(struct rpcif *rpc) ...@@ -378,37 +423,36 @@ int rpcif_manual_xfer(struct rpcif *rpc)
regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
smenr = rpc->enable; smenr = rpc->enable;
switch (rpc->dir) { switch (rpc->dir) {
case RPCIF_DATA_OUT: case RPCIF_DATA_OUT:
while (pos < rpc->xferlen) { while (pos < rpc->xferlen) {
u32 nbytes = rpc->xferlen - pos; u32 bytes_left = rpc->xferlen - pos;
u32 data[2]; u32 nbytes, data[2];
smcr = rpc->smcr | RPCIF_SMCR_SPIE; smcr = rpc->smcr | RPCIF_SMCR_SPIE;
if (nbytes > max) {
nbytes = max; /* nbytes may only be 1, 2, 4, or 8 */
nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
if (bytes_left > nbytes)
smcr |= RPCIF_SMCR_SSLKP; smcr |= RPCIF_SMCR_SSLKP;
}
smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
memcpy(data, rpc->buffer + pos, nbytes); memcpy(data, rpc->buffer + pos, nbytes);
if (nbytes > 4) { if (nbytes == 8) {
regmap_write(rpc->regmap, RPCIF_SMWDR1, regmap_write(rpc->regmap, RPCIF_SMWDR1,
data[0]); data[0]);
regmap_write(rpc->regmap, RPCIF_SMWDR0, regmap_write(rpc->regmap, RPCIF_SMWDR0,
data[1]); data[1]);
} else if (nbytes > 2) { } else {
regmap_write(rpc->regmap, RPCIF_SMWDR0, regmap_write(rpc->regmap, RPCIF_SMWDR0,
data[0]); data[0]);
} else {
regmap_write(rpc->regmap, RPCIF_SMWDR0,
data[0] << 16);
} }
regmap_write(rpc->regmap, RPCIF_SMADR,
rpc->smadr + pos);
regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
regmap_write(rpc->regmap, RPCIF_SMCR, smcr); regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
ret = wait_msg_xfer_end(rpc); ret = wait_msg_xfer_end(rpc);
if (ret) if (ret)
...@@ -448,14 +492,16 @@ int rpcif_manual_xfer(struct rpcif *rpc) ...@@ -448,14 +492,16 @@ int rpcif_manual_xfer(struct rpcif *rpc)
break; break;
} }
while (pos < rpc->xferlen) { while (pos < rpc->xferlen) {
u32 nbytes = rpc->xferlen - pos; u32 bytes_left = rpc->xferlen - pos;
u32 data[2]; u32 nbytes, data[2];
if (nbytes > max) /* nbytes may only be 1, 2, 4, or 8 */
nbytes = max; nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
regmap_write(rpc->regmap, RPCIF_SMADR, regmap_write(rpc->regmap, RPCIF_SMADR,
rpc->smadr + pos); rpc->smadr + pos);
smenr &= ~RPCIF_SMENR_SPIDE(0xF);
smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
regmap_write(rpc->regmap, RPCIF_SMENR, smenr); regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
regmap_write(rpc->regmap, RPCIF_SMCR, regmap_write(rpc->regmap, RPCIF_SMCR,
rpc->smcr | RPCIF_SMCR_SPIE); rpc->smcr | RPCIF_SMCR_SPIE);
...@@ -463,18 +509,14 @@ int rpcif_manual_xfer(struct rpcif *rpc) ...@@ -463,18 +509,14 @@ int rpcif_manual_xfer(struct rpcif *rpc)
if (ret) if (ret)
goto err_out; goto err_out;
if (nbytes > 4) { if (nbytes == 8) {
regmap_read(rpc->regmap, RPCIF_SMRDR1, regmap_read(rpc->regmap, RPCIF_SMRDR1,
&data[0]); &data[0]);
regmap_read(rpc->regmap, RPCIF_SMRDR0, regmap_read(rpc->regmap, RPCIF_SMRDR0,
&data[1]); &data[1]);
} else if (nbytes > 2) { } else {
regmap_read(rpc->regmap, RPCIF_SMRDR0,
&data[0]);
} else {
regmap_read(rpc->regmap, RPCIF_SMRDR0, regmap_read(rpc->regmap, RPCIF_SMRDR0,
&data[0]); &data[0]);
data[0] >>= 16;
} }
memcpy(rpc->buffer + pos, data, nbytes); memcpy(rpc->buffer + pos, data, nbytes);
...@@ -502,6 +544,48 @@ int rpcif_manual_xfer(struct rpcif *rpc) ...@@ -502,6 +544,48 @@ int rpcif_manual_xfer(struct rpcif *rpc)
} }
EXPORT_SYMBOL(rpcif_manual_xfer); EXPORT_SYMBOL(rpcif_manual_xfer);
static void memcpy_fromio_readw(void *to,
const void __iomem *from,
size_t count)
{
const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
u8 buf[2];
if (count && ((unsigned long)from & 1)) {
*(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
*(u8 *)to = buf[1];
from++;
to++;
count--;
}
while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
*(u16 *)to = __raw_readw(from);
from += 2;
to += 2;
count -= 2;
}
while (count >= maxw) {
#ifdef CONFIG_64BIT
*(u64 *)to = __raw_readq(from);
#else
*(u32 *)to = __raw_readl(from);
#endif
from += maxw;
to += maxw;
count -= maxw;
}
while (count >= 2) {
*(u16 *)to = __raw_readw(from);
from += 2;
to += 2;
count -= 2;
}
if (count) {
*(u16 *)buf = __raw_readw(from);
*(u8 *)to = buf[0];
}
}
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
{ {
loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1); loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
...@@ -523,7 +607,10 @@ ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) ...@@ -523,7 +607,10 @@ ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
memcpy_fromio(buf, rpc->dirmap + from, len); if (rpc->bus_size == 2)
memcpy_fromio_readw(buf, rpc->dirmap + from, len);
else
memcpy_fromio(buf, rpc->dirmap + from, len);
pm_runtime_put(rpc->dev); pm_runtime_put(rpc->dev);
......
...@@ -14,11 +14,12 @@ config EXYNOS5422_DMC ...@@ -14,11 +14,12 @@ config EXYNOS5422_DMC
depends on DEVFREQ_GOV_SIMPLE_ONDEMAND depends on DEVFREQ_GOV_SIMPLE_ONDEMAND
depends on (PM_DEVFREQ && PM_DEVFREQ_EVENT) depends on (PM_DEVFREQ && PM_DEVFREQ_EVENT)
help help
This adds driver for Exynos5422 DMC (Dynamic Memory Controller). This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
The driver provides support for Dynamic Voltage and Frequency Scaling in Controller). The driver provides support for Dynamic Voltage and
DMC and DRAM. It also supports changing timings of DRAM running with Frequency Scaling in DMC and DRAM. It also supports changing timings
different frequency. The timings are calculated based on DT memory of DRAM running with different frequency. The timings are calculated
information. based on DT memory information.
If unsure, say Y on devices with Samsung Exynos SoCs.
config EXYNOS_SROM config EXYNOS_SROM
bool "Exynos SROM controller driver" if COMPILE_TEST bool "Exynos SROM controller driver" if COMPILE_TEST
...@@ -29,6 +30,6 @@ config EXYNOS_SROM ...@@ -29,6 +30,6 @@ config EXYNOS_SROM
during suspend. If however appropriate device tree configuration during suspend. If however appropriate device tree configuration
is provided, the driver enables support for external memory is provided, the driver enables support for external memory
or external devices. or external devices.
If unsure, say Y on devices with Samsung Exynos SocS. If unsure, say Y on devices with Samsung Exynos SoCs.
endif endif
...@@ -16,6 +16,7 @@ config TEGRA20_EMC ...@@ -16,6 +16,7 @@ config TEGRA20_EMC
depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
select DEVFREQ_GOV_SIMPLE_ONDEMAND select DEVFREQ_GOV_SIMPLE_ONDEMAND
select PM_DEVFREQ select PM_DEVFREQ
select DDR
help help
This driver is for the External Memory Controller (EMC) found on This driver is for the External Memory Controller (EMC) found on
Tegra20 chips. The EMC controls the external DRAM on the board. Tegra20 chips. The EMC controls the external DRAM on the board.
......
...@@ -87,11 +87,9 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) ...@@ -87,11 +87,9 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
return ERR_PTR(-EPROBE_DEFER); return ERR_PTR(-EPROBE_DEFER);
} }
err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc); err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc);
if (err) { if (err)
put_device(mc->dev);
return ERR_PTR(err); return ERR_PTR(err);
}
return mc; return mc;
} }
...@@ -706,15 +704,6 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) ...@@ -706,15 +704,6 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc)
goto remove_nodes; goto remove_nodes;
} }
/*
* MC driver is registered too early, so early that generic driver
* syncing doesn't work for the MC. But it doesn't really matter
* since syncing works for the EMC drivers, hence we can sync the
* MC driver by ourselves and then EMC will complete syncing of
* the whole ICC state.
*/
icc_sync_state(mc->dev);
return 0; return 0;
remove_nodes: remove_nodes:
...@@ -835,6 +824,15 @@ static int __maybe_unused tegra_mc_resume(struct device *dev) ...@@ -835,6 +824,15 @@ static int __maybe_unused tegra_mc_resume(struct device *dev)
return 0; return 0;
} }
static void tegra_mc_sync_state(struct device *dev)
{
struct tegra_mc *mc = dev_get_drvdata(dev);
/* check whether ICC provider is registered */
if (mc->provider.dev == dev)
icc_sync_state(dev);
}
static const struct dev_pm_ops tegra_mc_pm_ops = { static const struct dev_pm_ops tegra_mc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume)
}; };
...@@ -845,6 +843,7 @@ static struct platform_driver tegra_mc_driver = { ...@@ -845,6 +843,7 @@ static struct platform_driver tegra_mc_driver = {
.of_match_table = tegra_mc_of_match, .of_match_table = tegra_mc_of_match,
.pm = &tegra_mc_pm_ops, .pm = &tegra_mc_pm_ops,
.suppress_bind_attrs = true, .suppress_bind_attrs = true,
.sync_state = tegra_mc_sync_state,
}, },
.prevent_deferred_probe = true, .prevent_deferred_probe = true,
.probe = tegra_mc_probe, .probe = tegra_mc_probe,
......
...@@ -197,6 +197,11 @@ static int tegra186_emc_probe(struct platform_device *pdev) ...@@ -197,6 +197,11 @@ static int tegra186_emc_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err);
goto put_bpmp; goto put_bpmp;
} }
if (msg.rx.ret < 0) {
err = -EINVAL;
dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
goto put_bpmp;
}
emc->debugfs.min_rate = ULONG_MAX; emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0; emc->debugfs.max_rate = 0;
......
This diff is collapsed.
...@@ -478,7 +478,7 @@ static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 type, ...@@ -478,7 +478,7 @@ static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 type,
static u32 tegra210_emc_r21021_periodic_compensation(struct tegra210_emc *emc) static u32 tegra210_emc_r21021_periodic_compensation(struct tegra210_emc *emc)
{ {
u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value; u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value;
u32 list[] = { static const u32 list[] = {
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2,
......
...@@ -1662,7 +1662,7 @@ static int tegra210_emc_debug_min_rate_set(void *data, u64 rate) ...@@ -1662,7 +1662,7 @@ static int tegra210_emc_debug_min_rate_set(void *data, u64 rate)
return 0; return 0;
} }
DEFINE_SIMPLE_ATTRIBUTE(tegra210_emc_debug_min_rate_fops, DEFINE_DEBUGFS_ATTRIBUTE(tegra210_emc_debug_min_rate_fops,
tegra210_emc_debug_min_rate_get, tegra210_emc_debug_min_rate_get,
tegra210_emc_debug_min_rate_set, "%llu\n"); tegra210_emc_debug_min_rate_set, "%llu\n");
...@@ -1692,7 +1692,7 @@ static int tegra210_emc_debug_max_rate_set(void *data, u64 rate) ...@@ -1692,7 +1692,7 @@ static int tegra210_emc_debug_max_rate_set(void *data, u64 rate)
return 0; return 0;
} }
DEFINE_SIMPLE_ATTRIBUTE(tegra210_emc_debug_max_rate_fops, DEFINE_DEBUGFS_ATTRIBUTE(tegra210_emc_debug_max_rate_fops,
tegra210_emc_debug_max_rate_get, tegra210_emc_debug_max_rate_get,
tegra210_emc_debug_max_rate_set, "%llu\n"); tegra210_emc_debug_max_rate_set, "%llu\n");
...@@ -1723,7 +1723,7 @@ static int tegra210_emc_debug_temperature_set(void *data, u64 temperature) ...@@ -1723,7 +1723,7 @@ static int tegra210_emc_debug_temperature_set(void *data, u64 temperature)
return 0; return 0;
} }
DEFINE_SIMPLE_ATTRIBUTE(tegra210_emc_debug_temperature_fops, DEFINE_DEBUGFS_ATTRIBUTE(tegra210_emc_debug_temperature_fops,
tegra210_emc_debug_temperature_get, tegra210_emc_debug_temperature_get,
tegra210_emc_debug_temperature_set, "%llu\n"); tegra210_emc_debug_temperature_set, "%llu\n");
......
...@@ -1289,7 +1289,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) ...@@ -1289,7 +1289,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
return 0; return 0;
} }
DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops, DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
tegra_emc_debug_min_rate_get, tegra_emc_debug_min_rate_get,
tegra_emc_debug_min_rate_set, "%llu\n"); tegra_emc_debug_min_rate_set, "%llu\n");
...@@ -1319,7 +1319,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) ...@@ -1319,7 +1319,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
return 0; return 0;
} }
DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops, DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
tegra_emc_debug_max_rate_get, tegra_emc_debug_max_rate_get,
tegra_emc_debug_max_rate_set, "%llu\n"); tegra_emc_debug_max_rate_set, "%llu\n");
......
...@@ -505,6 +505,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate); ...@@ -505,6 +505,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate);
static const struct of_device_id reserved_mem_matches[] = { static const struct of_device_id reserved_mem_matches[] = {
{ .compatible = "qcom,rmtfs-mem" }, { .compatible = "qcom,rmtfs-mem" },
{ .compatible = "qcom,cmd-db" }, { .compatible = "qcom,cmd-db" },
{ .compatible = "qcom,smem" },
{ .compatible = "ramoops" }, { .compatible = "ramoops" },
{ .compatible = "nvmem-rmem" }, { .compatible = "nvmem-rmem" },
{} {}
......
...@@ -58,7 +58,7 @@ config RESET_BRCMSTB ...@@ -58,7 +58,7 @@ config RESET_BRCMSTB
a SUN_TOP_CTRL_SW_INIT style controller. a SUN_TOP_CTRL_SW_INIT style controller.
config RESET_BRCMSTB_RESCAL config RESET_BRCMSTB_RESCAL
bool "Broadcom STB RESCAL reset controller" tristate "Broadcom STB RESCAL reset controller"
depends on HAS_IOMEM depends on HAS_IOMEM
depends on ARCH_BRCMSTB || COMPILE_TEST depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB default ARCH_BRCMSTB
...@@ -116,7 +116,7 @@ config RESET_LPC18XX ...@@ -116,7 +116,7 @@ config RESET_LPC18XX
config RESET_MCHP_SPARX5 config RESET_MCHP_SPARX5
bool "Microchip Sparx5 reset driver" bool "Microchip Sparx5 reset driver"
depends on ARCH_SPARX5 || COMPILE_TEST depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
default y if SPARX5_SWITCH default y if SPARX5_SWITCH
select MFD_SYSCON select MFD_SYSCON
help help
......
...@@ -13,15 +13,18 @@ ...@@ -13,15 +13,18 @@
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/reset-controller.h> #include <linux/reset-controller.h>
#define PROTECT_REG 0x84 struct reset_props {
#define PROTECT_BIT BIT(10) u32 protect_reg;
#define SOFT_RESET_REG 0x00 u32 protect_bit;
#define SOFT_RESET_BIT BIT(1) u32 reset_reg;
u32 reset_bit;
};
struct mchp_reset_context { struct mchp_reset_context {
struct regmap *cpu_ctrl; struct regmap *cpu_ctrl;
struct regmap *gcb_ctrl; struct regmap *gcb_ctrl;
struct reset_controller_dev rcdev; struct reset_controller_dev rcdev;
const struct reset_props *props;
}; };
static struct regmap_config sparx5_reset_regmap_config = { static struct regmap_config sparx5_reset_regmap_config = {
...@@ -38,14 +41,16 @@ static int sparx5_switch_reset(struct reset_controller_dev *rcdev, ...@@ -38,14 +41,16 @@ static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
u32 val; u32 val;
/* Make sure the core is PROTECTED from reset */ /* Make sure the core is PROTECTED from reset */
regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
ctx->props->protect_bit, ctx->props->protect_bit);
/* Start soft reset */ /* Start soft reset */
regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg,
ctx->props->reset_bit);
/* Wait for soft reset done */ /* Wait for soft reset done */
return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val,
(val & SOFT_RESET_BIT) == 0, (val & ctx->props->reset_bit) == 0,
1, 100); 1, 100);
} }
...@@ -115,13 +120,32 @@ static int mchp_sparx5_reset_probe(struct platform_device *pdev) ...@@ -115,13 +120,32 @@ static int mchp_sparx5_reset_probe(struct platform_device *pdev)
ctx->rcdev.nr_resets = 1; ctx->rcdev.nr_resets = 1;
ctx->rcdev.ops = &sparx5_reset_ops; ctx->rcdev.ops = &sparx5_reset_ops;
ctx->rcdev.of_node = dn; ctx->rcdev.of_node = dn;
ctx->props = device_get_match_data(&pdev->dev);
return devm_reset_controller_register(&pdev->dev, &ctx->rcdev); return devm_reset_controller_register(&pdev->dev, &ctx->rcdev);
} }
static const struct reset_props reset_props_sparx5 = {
.protect_reg = 0x84,
.protect_bit = BIT(10),
.reset_reg = 0x0,
.reset_bit = BIT(1),
};
static const struct reset_props reset_props_lan966x = {
.protect_reg = 0x88,
.protect_bit = BIT(5),
.reset_reg = 0x0,
.reset_bit = BIT(1),
};
static const struct of_device_id mchp_sparx5_reset_of_match[] = { static const struct of_device_id mchp_sparx5_reset_of_match[] = {
{ {
.compatible = "microchip,sparx5-switch-reset", .compatible = "microchip,sparx5-switch-reset",
.data = &reset_props_sparx5,
}, {
.compatible = "microchip,lan966x-switch-reset",
.data = &reset_props_lan966x,
}, },
{ } { }
}; };
......
...@@ -155,6 +155,10 @@ static const struct of_device_id uniphier_glue_reset_match[] = { ...@@ -155,6 +155,10 @@ static const struct of_device_id uniphier_glue_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-usb3-reset", .compatible = "socionext,uniphier-pxs3-usb3-reset",
.data = &uniphier_pxs2_data, .data = &uniphier_pxs2_data,
}, },
{
.compatible = "socionext,uniphier-nx1-usb3-reset",
.data = &uniphier_pxs2_data,
},
{ {
.compatible = "socionext,uniphier-pro4-ahci-reset", .compatible = "socionext,uniphier-pro4-ahci-reset",
.data = &uniphier_pro4_data, .data = &uniphier_pro4_data,
......
...@@ -136,6 +136,21 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { ...@@ -136,6 +136,21 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */ UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */
UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */ UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */
UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */ UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */
UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
UNIPHIER_RESET_END,
};
static const struct uniphier_reset_data uniphier_nx1_sys_reset_data[] = {
UNIPHIER_RESETX(4, 0x2008, 8), /* eMMC */
UNIPHIER_RESETX(6, 0x200c, 0), /* Ether */
UNIPHIER_RESETX(12, 0x200c, 16), /* USB30 link */
UNIPHIER_RESETX(16, 0x200c, 24), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 25), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 26), /* USB30-PHY2 */
UNIPHIER_RESETX(24, 0x200c, 8), /* PCIe */
UNIPHIER_RESETX(52, 0x2010, 0), /* VOC */
UNIPHIER_RESETX(58, 0x2010, 8), /* HDMI-Tx */
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
...@@ -400,6 +415,10 @@ static const struct of_device_id uniphier_reset_match[] = { ...@@ -400,6 +415,10 @@ static const struct of_device_id uniphier_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-reset", .compatible = "socionext,uniphier-pxs3-reset",
.data = uniphier_pxs3_sys_reset_data, .data = uniphier_pxs3_sys_reset_data,
}, },
{
.compatible = "socionext,uniphier-nx1-reset",
.data = uniphier_nx1_sys_reset_data,
},
/* Media I/O reset, SD reset */ /* Media I/O reset, SD reset */
{ {
.compatible = "socionext,uniphier-ld4-mio-reset", .compatible = "socionext,uniphier-ld4-mio-reset",
...@@ -437,6 +456,10 @@ static const struct of_device_id uniphier_reset_match[] = { ...@@ -437,6 +456,10 @@ static const struct of_device_id uniphier_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-sd-reset", .compatible = "socionext,uniphier-pxs3-sd-reset",
.data = uniphier_pro5_sd_reset_data, .data = uniphier_pro5_sd_reset_data,
}, },
{
.compatible = "socionext,uniphier-nx1-sd-reset",
.data = uniphier_pro5_sd_reset_data,
},
/* Peripheral reset */ /* Peripheral reset */
{ {
.compatible = "socionext,uniphier-ld4-peri-reset", .compatible = "socionext,uniphier-ld4-peri-reset",
...@@ -470,6 +493,10 @@ static const struct of_device_id uniphier_reset_match[] = { ...@@ -470,6 +493,10 @@ static const struct of_device_id uniphier_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-peri-reset", .compatible = "socionext,uniphier-pxs3-peri-reset",
.data = uniphier_pro4_peri_reset_data, .data = uniphier_pro4_peri_reset_data,
}, },
{
.compatible = "socionext,uniphier-nx1-peri-reset",
.data = uniphier_pro4_peri_reset_data,
},
/* Analog signal amplifiers reset */ /* Analog signal amplifiers reset */
{ {
.compatible = "socionext,uniphier-ld11-adamv-reset", .compatible = "socionext,uniphier-ld11-adamv-reset",
......
...@@ -1404,16 +1404,10 @@ config RTC_DRV_OMAP ...@@ -1404,16 +1404,10 @@ config RTC_DRV_OMAP
This driver can also be built as a module, if so, module This driver can also be built as a module, if so, module
will be called rtc-omap. will be called rtc-omap.
config HAVE_S3C_RTC
bool
help
This will include RTC support for Samsung SoCs. If
you want to include RTC support for any machine, kindly
select this in the respective mach-XXXX/Kconfig file.
config RTC_DRV_S3C config RTC_DRV_S3C
tristate "Samsung S3C series SoC RTC" tristate "Samsung S3C series SoC RTC"
depends on ARCH_S3C64XX || HAVE_S3C_RTC || COMPILE_TEST depends on ARCH_EXYNOS || ARCH_S3C64XX || ARCH_S3C24XX || ARCH_S5PV210 || \
COMPILE_TEST
help help
RTC (Realtime Clock) driver for the clock inbuilt into the RTC (Realtime Clock) driver for the clock inbuilt into the
Samsung S3C24XX series of SoCs. This can provide periodic Samsung S3C24XX series of SoCs. This can provide periodic
......
...@@ -168,7 +168,6 @@ EXPORT_SYMBOL_GPL(meson_canvas_free); ...@@ -168,7 +168,6 @@ EXPORT_SYMBOL_GPL(meson_canvas_free);
static int meson_canvas_probe(struct platform_device *pdev) static int meson_canvas_probe(struct platform_device *pdev)
{ {
struct resource *res;
struct meson_canvas *canvas; struct meson_canvas *canvas;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
...@@ -176,8 +175,7 @@ static int meson_canvas_probe(struct platform_device *pdev) ...@@ -176,8 +175,7 @@ static int meson_canvas_probe(struct platform_device *pdev)
if (!canvas) if (!canvas)
return -ENOMEM; return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); canvas->reg_base = devm_platform_ioremap_resource(pdev, 0);
canvas->reg_base = devm_ioremap_resource(dev, res);
if (IS_ERR(canvas->reg_base)) if (IS_ERR(canvas->reg_base))
return PTR_ERR(canvas->reg_base); return PTR_ERR(canvas->reg_base);
......
...@@ -606,7 +606,6 @@ static int meson_msr_probe(struct platform_device *pdev) ...@@ -606,7 +606,6 @@ static int meson_msr_probe(struct platform_device *pdev)
{ {
const struct meson_msr_id *match_data; const struct meson_msr_id *match_data;
struct meson_msr *priv; struct meson_msr *priv;
struct resource *res;
struct dentry *root, *clks; struct dentry *root, *clks;
void __iomem *base; void __iomem *base;
int i; int i;
...@@ -624,8 +623,7 @@ static int meson_msr_probe(struct platform_device *pdev) ...@@ -624,8 +623,7 @@ static int meson_msr_probe(struct platform_device *pdev)
memcpy(priv->msr_table, match_data, sizeof(priv->msr_table)); memcpy(priv->msr_table, match_data, sizeof(priv->msr_table));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_platform_ioremap_resource(pdev, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base)) if (IS_ERR(base))
return PTR_ERR(base); return PTR_ERR(base);
......
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