Commit d60c98c2 authored by Kukjin Kim's avatar Kukjin Kim

Merge branch 'for-spi' into s5p-fixes-for-linus

parents 8fa9dd04 30757414
...@@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { ...@@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
.cfg_gpio = s3c64xx_spi_cfg_gpio, .cfg_gpio = s3c64xx_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13, .rx_lvl_offset = 13,
.tx_st_done = 21,
}; };
static u64 spi_dmamask = DMA_BIT_MASK(32); static u64 spi_dmamask = DMA_BIT_MASK(32);
...@@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { ...@@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
.cfg_gpio = s3c64xx_spi_cfg_gpio, .cfg_gpio = s3c64xx_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13, .rx_lvl_offset = 13,
.tx_st_done = 21,
}; };
struct platform_device s3c64xx_device_spi1 = { struct platform_device s3c64xx_device_spi1 = {
......
...@@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = { ...@@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
.cfg_gpio = s5p6440_spi_cfg_gpio, .cfg_gpio = s5p6440_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff, .fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15, .rx_lvl_offset = 15,
.tx_st_done = 25,
}; };
static struct s3c64xx_spi_info s5p6450_spi0_pdata = { static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
.cfg_gpio = s5p6450_spi_cfg_gpio, .cfg_gpio = s5p6450_spi_cfg_gpio,
.fifo_lvl_mask = 0x1ff, .fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15, .rx_lvl_offset = 15,
.tx_st_done = 25,
}; };
static u64 spi_dmamask = DMA_BIT_MASK(32); static u64 spi_dmamask = DMA_BIT_MASK(32);
...@@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = { ...@@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
.cfg_gpio = s5p6440_spi_cfg_gpio, .cfg_gpio = s5p6440_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 15, .rx_lvl_offset = 15,
.tx_st_done = 25,
}; };
static struct s3c64xx_spi_info s5p6450_spi1_pdata = { static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
.cfg_gpio = s5p6450_spi_cfg_gpio, .cfg_gpio = s5p6450_spi_cfg_gpio,
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 15, .rx_lvl_offset = 15,
.tx_st_done = 25,
}; };
struct platform_device s5p64x0_device_spi1 = { struct platform_device s5p64x0_device_spi1 = {
......
...@@ -91,6 +91,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = { ...@@ -91,6 +91,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13, .rx_lvl_offset = 13,
.high_speed = 1, .high_speed = 1,
.tx_st_done = 21,
}; };
static u64 spi_dmamask = DMA_BIT_MASK(32); static u64 spi_dmamask = DMA_BIT_MASK(32);
...@@ -135,6 +136,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = { ...@@ -135,6 +136,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13, .rx_lvl_offset = 13,
.high_speed = 1, .high_speed = 1,
.tx_st_done = 21,
}; };
struct platform_device s5pc100_device_spi1 = { struct platform_device s5pc100_device_spi1 = {
...@@ -177,6 +179,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = { ...@@ -177,6 +179,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 13, .rx_lvl_offset = 13,
.high_speed = 1, .high_speed = 1,
.tx_st_done = 21,
}; };
struct platform_device s5pc100_device_spi2 = { struct platform_device s5pc100_device_spi2 = {
......
...@@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = { ...@@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
.fifo_lvl_mask = 0x1ff, .fifo_lvl_mask = 0x1ff,
.rx_lvl_offset = 15, .rx_lvl_offset = 15,
.high_speed = 1, .high_speed = 1,
.tx_st_done = 25,
}; };
static u64 spi_dmamask = DMA_BIT_MASK(32); static u64 spi_dmamask = DMA_BIT_MASK(32);
...@@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = { ...@@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
.fifo_lvl_mask = 0x7f, .fifo_lvl_mask = 0x7f,
.rx_lvl_offset = 15, .rx_lvl_offset = 15,
.high_speed = 1, .high_speed = 1,
.tx_st_done = 25,
}; };
struct platform_device s5pv210_device_spi1 = { struct platform_device s5pv210_device_spi1 = {
......
...@@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo { ...@@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo {
* @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
* @rx_lvl_offset: Depends on tx fifo_lvl field and bus number * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
* @high_speed: If the controller supports HIGH_SPEED_EN bit * @high_speed: If the controller supports HIGH_SPEED_EN bit
* @tx_st_done: Depends on tx fifo_lvl field
*/ */
struct s3c64xx_spi_info { struct s3c64xx_spi_info {
int src_clk_nr; int src_clk_nr;
...@@ -53,6 +54,7 @@ struct s3c64xx_spi_info { ...@@ -53,6 +54,7 @@ struct s3c64xx_spi_info {
int fifo_lvl_mask; int fifo_lvl_mask;
int rx_lvl_offset; int rx_lvl_offset;
int high_speed; int high_speed;
int tx_st_done;
}; };
/** /**
......
...@@ -116,9 +116,7 @@ ...@@ -116,9 +116,7 @@
(((i)->fifo_lvl_mask + 1))) \ (((i)->fifo_lvl_mask + 1))) \
? 1 : 0) ? 1 : 0)
#define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \ #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
(((i)->fifo_lvl_mask + 1) << 1)) \
? 1 : 0)
#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
......
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