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Commit d7c6dbc0 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'memory-controller-drv-5.9-2' of... 

Merge tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.9, part 2

1. Minor cleanups and fixes of multiple memory controller drivers,
   mostly around code quality and readability,
2. Add Git repository to drivers/memory entry in MAINTAINERS,
3. Allow MIPS jz4780 FUSE driver to probe by removing conflicting memory
   region with jz4780_nemc.

* tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: jz4780_nemc: Only request IO memory the driver will use
  MAINTAINERS: Add Git repository for memory controller drivers
  memory: brcmstb_dpfe: Fix language typo
  memory: samsung: exynos5422-dmc: Correct white space issues
  memory: samsung: exynos-srom: Correct alignment
  memory: pl172: Enclose macro argument usage in parenthesis
  memory: of: Correct kerneldoc
  memory: omap-gpmc: Fix language typo
  memory: omap-gpmc: Correct white space issues
  memory: omap-gpmc: Use 'unsigned int' for consistency
  memory: omap-gpmc: Enclose macro argument usage in parenthesis
  memory: omap-gpmc: Correct kerneldoc
  memory: mvebu-devbus: Align with open parenthesis
  memory: mvebu-devbus: Add missing braces to all arms of if statement
  memory: bt1-l2-ctl: Add blank lines after declarations

Link: https://lore.kernel.org/r/20200729163008.5820-1-krzk@kernel.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9c52a264 f046e4a3
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Showing with 75 additions and 68 deletions
MAINTAINERS
View file @ d7c6dbc0
...@@ -11089,6 +11089,7 @@ MEMORY CONTROLLER DRIVERS ...@@ -11089,6 +11089,7 @@ MEMORY CONTROLLER DRIVERS
M: Krzysztof Kozlowski <krzk@kernel.org> M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-kernel@vger.kernel.org L: linux-kernel@vger.kernel.org
S: Maintained S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
F: Documentation/devicetree/bindings/memory-controllers/ F: Documentation/devicetree/bindings/memory-controllers/
F: drivers/memory/ F: drivers/memory/
......
drivers/memory/brcmstb_dpfe.c
View file @ d7c6dbc0
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
* - BE kernel + LE firmware image * - BE kernel + LE firmware image
* - BE kernel + BE firmware image * - BE kernel + BE firmware image
* *
* The DPCU always runs in big endian mode. The firwmare image, however, can * The DPCU always runs in big endian mode. The firmware image, however, can
* be in either format. Also, communication between host CPU and DCPU is * be in either format. Also, communication between host CPU and DCPU is
* always in little endian. * always in little endian.
*/ */
......
drivers/memory/bt1-l2-ctl.c
View file @ d7c6dbc0
...@@ -66,6 +66,7 @@ struct l2_ctl_device_attribute { ...@@ -66,6 +66,7 @@ struct l2_ctl_device_attribute {
struct device_attribute dev_attr; struct device_attribute dev_attr;
enum l2_ctl_stall id; enum l2_ctl_stall id;
}; };
#define to_l2_ctl_dev_attr(_dev_attr) \ #define to_l2_ctl_dev_attr(_dev_attr) \
container_of(_dev_attr, struct l2_ctl_device_attribute, dev_attr) container_of(_dev_attr, struct l2_ctl_device_attribute, dev_attr)
...@@ -242,6 +243,7 @@ static ssize_t l2_ctl_latency_store(struct device *dev, ...@@ -242,6 +243,7 @@ static ssize_t l2_ctl_latency_store(struct device *dev,
return count; return count;
} }
static L2_CTL_ATTR_RW(l2_ws_latency, l2_ctl_latency, L2_WS_STALL); static L2_CTL_ATTR_RW(l2_ws_latency, l2_ctl_latency, L2_WS_STALL);
static L2_CTL_ATTR_RW(l2_tag_latency, l2_ctl_latency, L2_TAG_STALL); static L2_CTL_ATTR_RW(l2_tag_latency, l2_ctl_latency, L2_TAG_STALL);
static L2_CTL_ATTR_RW(l2_data_latency, l2_ctl_latency, L2_DATA_STALL); static L2_CTL_ATTR_RW(l2_data_latency, l2_ctl_latency, L2_DATA_STALL);
......
drivers/memory/jz4780-nemc.c
View file @ d7c6dbc0
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h>
#include <linux/math64.h> #include <linux/math64.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
...@@ -22,6 +23,8 @@ ...@@ -22,6 +23,8 @@
#define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4)) #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
#define NEMC_NFCSR 0x50 #define NEMC_NFCSR 0x50
#define NEMC_REG_LEN 0x54
#define NEMC_SMCR_SMT BIT(0) #define NEMC_SMCR_SMT BIT(0)
#define NEMC_SMCR_BW_SHIFT 6 #define NEMC_SMCR_BW_SHIFT 6
#define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT) #define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
...@@ -288,7 +291,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev) ...@@ -288,7 +291,19 @@ static int jz4780_nemc_probe(struct platform_device *pdev)
nemc->dev = dev; nemc->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nemc->base = devm_ioremap_resource(dev, res);
/*
* The driver currently only uses the registers up to offset
* NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
* NEMC registers, we only request the registers we will use for now;
* that way the EFUSE driver can probe too.
*/
if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
dev_err(dev, "unable to request I/O memory region\n");
return -EBUSY;
}
nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
if (IS_ERR(nemc->base)) { if (IS_ERR(nemc->base)) {
dev_err(dev, "failed to get I/O memory\n"); dev_err(dev, "failed to get I/O memory\n");
return PTR_ERR(nemc->base); return PTR_ERR(nemc->base);
......
drivers/memory/mvebu-devbus.c
View file @ d7c6dbc0
...@@ -124,32 +124,32 @@ static int devbus_get_timing_params(struct devbus *devbus, ...@@ -124,32 +124,32 @@ static int devbus_get_timing_params(struct devbus *devbus,
* The bus width is encoded into the register as 0 for 8 bits, * The bus width is encoded into the register as 0 for 8 bits,
* and 1 for 16 bits, so we do the necessary conversion here. * and 1 for 16 bits, so we do the necessary conversion here.
*/ */
if (r->bus_width == 8) if (r->bus_width == 8) {
r->bus_width = 0; r->bus_width = 0;
else if (r->bus_width == 16) } else if (r->bus_width == 16) {
r->bus_width = 1; r->bus_width = 1;
else { } else {
dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width); dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
return -EINVAL; return -EINVAL;
} }
err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps", err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
&r->badr_skew); &r->badr_skew);
if (err < 0) if (err < 0)
return err; return err;
err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps", err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
&r->turn_off); &r->turn_off);
if (err < 0) if (err < 0)
return err; return err;
err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps", err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
&r->acc_first); &r->acc_first);
if (err < 0) if (err < 0)
return err; return err;
err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps", err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
&r->acc_next); &r->acc_next);
if (err < 0) if (err < 0)
return err; return err;
...@@ -175,17 +175,17 @@ static int devbus_get_timing_params(struct devbus *devbus, ...@@ -175,17 +175,17 @@ static int devbus_get_timing_params(struct devbus *devbus,
} }
err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps", err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
&w->ale_wr); &w->ale_wr);
if (err < 0) if (err < 0)
return err; return err;
err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps", err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
&w->wr_low); &w->wr_low);
if (err < 0) if (err < 0)
return err; return err;
err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps", err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
&w->wr_high); &w->wr_high);
if (err < 0) if (err < 0)
return err; return err;
......
drivers/memory/of_memory.c
View file @ d7c6dbc0
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
/** /**
* of_get_min_tck() - extract min timing values for ddr * of_get_min_tck() - extract min timing values for ddr
* @np: pointer to ddr device tree node * @np: pointer to ddr device tree node
* @device: device requesting for min timing values * @dev: device requesting for min timing values
* *
* Populates the lpddr2_min_tck structure by extracting data * Populates the lpddr2_min_tck structure by extracting data
* from device tree node. Returns a pointer to the populated * from device tree node. Returns a pointer to the populated
...@@ -155,7 +155,7 @@ EXPORT_SYMBOL(of_get_ddr_timings); ...@@ -155,7 +155,7 @@ EXPORT_SYMBOL(of_get_ddr_timings);
/** /**
* of_lpddr3_get_min_tck() - extract min timing values for lpddr3 * of_lpddr3_get_min_tck() - extract min timing values for lpddr3
* @np: pointer to ddr device tree node * @np: pointer to ddr device tree node
* @device: device requesting for min timing values * @dev: device requesting for min timing values
* *
* Populates the lpddr3_min_tck structure by extracting data * Populates the lpddr3_min_tck structure by extracting data
* from device tree node. Returns a pointer to the populated * from device tree node. Returns a pointer to the populated
......
drivers/memory/omap-gpmc.c
View file @ d7c6dbc0
...@@ -109,8 +109,8 @@ ...@@ -109,8 +109,8 @@
#define ENABLE_PREFETCH (0x1 << 7) #define ENABLE_PREFETCH (0x1 << 7)
#define DMA_MPU_MODE 2 #define DMA_MPU_MODE 2
#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
#define GPMC_REVISION_MINOR(l) (l & 0xf) #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
#define GPMC_HAS_WR_ACCESS 0x1 #define GPMC_HAS_WR_ACCESS 0x1
#define GPMC_HAS_WR_DATA_MUX_BUS 0x2 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
...@@ -141,27 +141,27 @@ ...@@ -141,27 +141,27 @@
#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
/** CLKACTIVATIONTIME Max Ticks */ /** CLKACTIVATIONTIME Max Ticks */
#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
/** ATTACHEDDEVICEPAGELENGTH Max Value */ /** ATTACHEDDEVICEPAGELENGTH Max Value */
#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18) #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
/** WAITMONITORINGTIME Max Ticks */ /** WAITMONITORINGTIME Max Ticks */
#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
/** DEVICESIZE Max Value */ /** DEVICESIZE Max Value */
#define GPMC_CONFIG1_DEVICESIZE_MAX 1 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
...@@ -246,7 +246,7 @@ static DEFINE_SPINLOCK(gpmc_mem_lock); ...@@ -246,7 +246,7 @@ static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned int gpmc_cs_num = GPMC_CS_NUM; static unsigned int gpmc_cs_num = GPMC_CS_NUM;
static unsigned int gpmc_nr_waitpins; static unsigned int gpmc_nr_waitpins;
static resource_size_t phys_base, mem_size; static resource_size_t phys_base, mem_size;
static unsigned gpmc_capability; static unsigned int gpmc_capability;
static void __iomem *gpmc_base; static void __iomem *gpmc_base;
static struct clk *gpmc_l3_clk; static struct clk *gpmc_l3_clk;
...@@ -292,15 +292,14 @@ static unsigned long gpmc_get_fclk_period(void) ...@@ -292,15 +292,14 @@ static unsigned long gpmc_get_fclk_period(void)
/** /**
* gpmc_get_clk_period - get period of selected clock domain in ps * gpmc_get_clk_period - get period of selected clock domain in ps
* @cs Chip Select Region. * @cs: Chip Select Region.
* @cd Clock Domain. * @cd: Clock Domain.
* *
* GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
* prior to calling this function with GPMC_CD_CLK. * prior to calling this function with GPMC_CD_CLK.
*/ */
static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
{ {
unsigned long tick_ps = gpmc_get_fclk_period(); unsigned long tick_ps = gpmc_get_fclk_period();
u32 l; u32 l;
int div; int div;
...@@ -320,7 +319,6 @@ static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) ...@@ -320,7 +319,6 @@ static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
} }
return tick_ps; return tick_ps;
} }
static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
...@@ -412,7 +410,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) ...@@ -412,7 +410,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
* @reg: GPMC_CS_CONFIGn register offset. * @reg: GPMC_CS_CONFIGn register offset.
* @st_bit: Start Bit * @st_bit: Start Bit
* @end_bit: End Bit. Must be >= @st_bit. * @end_bit: End Bit. Must be >= @st_bit.
* @ma:x Maximum parameter value (before optional @shift). * @max: Maximum parameter value (before optional @shift).
* If 0, maximum is as high as @st_bit and @end_bit allow. * If 0, maximum is as high as @st_bit and @end_bit allow.
* @name: DTS node name, w/o "gpmc," * @name: DTS node name, w/o "gpmc,"
* @cd: Clock Domain of timing parameter. * @cd: Clock Domain of timing parameter.
...@@ -512,7 +510,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc) ...@@ -512,7 +510,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc)
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
...@@ -626,9 +624,8 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max ...@@ -626,9 +624,8 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max
l = gpmc_cs_read_reg(cs, reg); l = gpmc_cs_read_reg(cs, reg);
#ifdef CONFIG_OMAP_GPMC_DEBUG #ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info( pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
(l >> st_bit) & mask, time); (l >> st_bit) & mask, time);
#endif #endif
l &= ~(mask << st_bit); l &= ~(mask << st_bit);
...@@ -663,7 +660,6 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max ...@@ -663,7 +660,6 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max
*/ */
static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
{ {
int div = gpmc_ns_to_ticks(wait_monitoring); int div = gpmc_ns_to_ticks(wait_monitoring);
div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
...@@ -675,7 +671,6 @@ static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) ...@@ -675,7 +671,6 @@ static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
div = 1; div = 1;
return div; return div;
} }
/** /**
...@@ -729,7 +724,6 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, ...@@ -729,7 +724,6 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
if (!s->sync_read && !s->sync_write && if (!s->sync_read && !s->sync_write &&
(s->wait_on_read || s->wait_on_write) (s->wait_on_read || s->wait_on_write)
) { ) {
div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
if (div < 0) { if (div < 0) {
pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
...@@ -1088,7 +1082,7 @@ static struct gpmc_nand_ops nand_ops = { ...@@ -1088,7 +1082,7 @@ static struct gpmc_nand_ops nand_ops = {
/** /**
* gpmc_omap_get_nand_ops - Get the GPMC NAND interface * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
* @regs: the GPMC NAND register map exclusive for NAND use. * @reg: the GPMC NAND register map exclusive for NAND use.
* @cs: GPMC chip select number on which the NAND sits. The * @cs: GPMC chip select number on which the NAND sits. The
* register map returned will be specific to this chip select. * register map returned will be specific to this chip select.
* *
...@@ -1243,7 +1237,7 @@ int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq, ...@@ -1243,7 +1237,7 @@ int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
} }
EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings); EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
int gpmc_get_client_irq(unsigned irq_config) int gpmc_get_client_irq(unsigned int irq_config)
{ {
if (!gpmc_irq_domain) { if (!gpmc_irq_domain) {
pr_warn("%s called before GPMC IRQ domain available\n", pr_warn("%s called before GPMC IRQ domain available\n",
...@@ -1466,7 +1460,6 @@ static void gpmc_mem_exit(void) ...@@ -1466,7 +1460,6 @@ static void gpmc_mem_exit(void)
continue; continue;
gpmc_cs_delete_mem(cs); gpmc_cs_delete_mem(cs);
} }
} }
static void gpmc_mem_init(void) static void gpmc_mem_init(void)
...@@ -1635,17 +1628,14 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, ...@@ -1635,17 +1628,14 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
/* oe_on */ /* oe_on */
temp = dev_t->t_oeasu; temp = dev_t->t_oeasu;
if (mux) if (mux)
temp = max_t(u32, temp, temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
gpmc_t->adv_rd_off + dev_t->t_aavdh);
gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
/* access */ /* access */
temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
gpmc_t->oe_on + dev_t->t_oe); gpmc_t->oe_on + dev_t->t_oe);
temp = max_t(u32, temp, temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
gpmc_t->cs_on + dev_t->t_ce); temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
temp = max_t(u32, temp,
gpmc_t->adv_on + dev_t->t_aa);
gpmc_t->access = gpmc_round_ps_to_ticks(temp); gpmc_t->access = gpmc_round_ps_to_ticks(temp);
gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
...@@ -2091,7 +2081,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, ...@@ -2091,7 +2081,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
gpmc_cs_disable_mem(cs); gpmc_cs_disable_mem(cs);
/* /*
* FIXME: gpmc_cs_request() will map the CS to an arbitary * FIXME: gpmc_cs_request() will map the CS to an arbitrary
* location in the gpmc address space. When booting with * location in the gpmc address space. When booting with
* device-tree we want the NOR flash to be mapped to the * device-tree we want the NOR flash to be mapped to the
* location specified in the device-tree blob. So remap the * location specified in the device-tree blob. So remap the
......
drivers/memory/pl172.c
View file @ d7c6dbc0
...@@ -21,7 +21,7 @@ ...@@ -21,7 +21,7 @@
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/time.h> #include <linux/time.h>
#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n) #define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
#define MPMC_STATIC_CFG_MW_8BIT 0x0 #define MPMC_STATIC_CFG_MW_8BIT 0x0
#define MPMC_STATIC_CFG_MW_16BIT 0x1 #define MPMC_STATIC_CFG_MW_16BIT 0x1
#define MPMC_STATIC_CFG_MW_32BIT 0x2 #define MPMC_STATIC_CFG_MW_32BIT 0x2
...@@ -31,17 +31,17 @@ ...@@ -31,17 +31,17 @@
#define MPMC_STATIC_CFG_EW BIT(8) #define MPMC_STATIC_CFG_EW BIT(8)
#define MPMC_STATIC_CFG_B BIT(19) #define MPMC_STATIC_CFG_B BIT(19)
#define MPMC_STATIC_CFG_P BIT(20) #define MPMC_STATIC_CFG_P BIT(20)
#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n) #define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
#define MPMC_STATIC_WAIT_WEN_MAX 0x0f #define MPMC_STATIC_WAIT_WEN_MAX 0x0f
#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n) #define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
#define MPMC_STATIC_WAIT_OEN_MAX 0x0f #define MPMC_STATIC_WAIT_OEN_MAX 0x0f
#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n) #define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
#define MPMC_STATIC_WAIT_RD_MAX 0x1f #define MPMC_STATIC_WAIT_RD_MAX 0x1f
#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n) #define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f #define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n) #define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
#define MPMC_STATIC_WAIT_WR_MAX 0x1f #define MPMC_STATIC_WAIT_WR_MAX 0x1f
#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n) #define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
#define MPMC_STATIC_WAIT_TURN_MAX 0x0f #define MPMC_STATIC_WAIT_TURN_MAX 0x0f
/* Maximum number of static chip selects */ /* Maximum number of static chip selects */
......
drivers/memory/samsung/exynos-srom.c
View file @ d7c6dbc0
...@@ -47,9 +47,9 @@ struct exynos_srom { ...@@ -47,9 +47,9 @@ struct exynos_srom {
struct exynos_srom_reg_dump *reg_offset; struct exynos_srom_reg_dump *reg_offset;
}; };
static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump( static struct exynos_srom_reg_dump *
const unsigned long *rdump, exynos_srom_alloc_reg_dump(const unsigned long *rdump,
unsigned long nr_rdump) unsigned long nr_rdump)
{ {
struct exynos_srom_reg_dump *rd; struct exynos_srom_reg_dump *rd;
unsigned int i; unsigned int i;
...@@ -116,7 +116,7 @@ static int exynos_srom_probe(struct platform_device *pdev) ...@@ -116,7 +116,7 @@ static int exynos_srom_probe(struct platform_device *pdev)
} }
srom = devm_kzalloc(&pdev->dev, srom = devm_kzalloc(&pdev->dev,
sizeof(struct exynos_srom), GFP_KERNEL); sizeof(struct exynos_srom), GFP_KERNEL);
if (!srom) if (!srom)
return -ENOMEM; return -ENOMEM;
...@@ -130,7 +130,7 @@ static int exynos_srom_probe(struct platform_device *pdev) ...@@ -130,7 +130,7 @@ static int exynos_srom_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, srom); platform_set_drvdata(pdev, srom);
srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets, srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
ARRAY_SIZE(exynos_srom_offsets)); ARRAY_SIZE(exynos_srom_offsets));
if (!srom->reg_offset) { if (!srom->reg_offset) {
iounmap(srom->reg_base); iounmap(srom->reg_base);
return -ENOMEM; return -ENOMEM;
...@@ -157,16 +157,16 @@ static int exynos_srom_probe(struct platform_device *pdev) ...@@ -157,16 +157,16 @@ static int exynos_srom_probe(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
static void exynos_srom_save(void __iomem *base, static void exynos_srom_save(void __iomem *base,
struct exynos_srom_reg_dump *rd, struct exynos_srom_reg_dump *rd,
unsigned int num_regs) unsigned int num_regs)
{ {
for (; num_regs > 0; --num_regs, ++rd) for (; num_regs > 0; --num_regs, ++rd)
rd->value = readl(base + rd->offset); rd->value = readl(base + rd->offset);
} }
static void exynos_srom_restore(void __iomem *base, static void exynos_srom_restore(void __iomem *base,
const struct exynos_srom_reg_dump *rd, const struct exynos_srom_reg_dump *rd,
unsigned int num_regs) unsigned int num_regs)
{ {
for (; num_regs > 0; --num_regs, ++rd) for (; num_regs > 0; --num_regs, ++rd)
writel(rd->value, base + rd->offset); writel(rd->value, base + rd->offset);
...@@ -177,7 +177,7 @@ static int exynos_srom_suspend(struct device *dev) ...@@ -177,7 +177,7 @@ static int exynos_srom_suspend(struct device *dev)
struct exynos_srom *srom = dev_get_drvdata(dev); struct exynos_srom *srom = dev_get_drvdata(dev);
exynos_srom_save(srom->reg_base, srom->reg_offset, exynos_srom_save(srom->reg_base, srom->reg_offset,
ARRAY_SIZE(exynos_srom_offsets)); ARRAY_SIZE(exynos_srom_offsets));
return 0; return 0;
} }
...@@ -186,7 +186,7 @@ static int exynos_srom_resume(struct device *dev) ...@@ -186,7 +186,7 @@ static int exynos_srom_resume(struct device *dev)
struct exynos_srom *srom = dev_get_drvdata(dev); struct exynos_srom *srom = dev_get_drvdata(dev);
exynos_srom_restore(srom->reg_base, srom->reg_offset, exynos_srom_restore(srom->reg_base, srom->reg_offset,
ARRAY_SIZE(exynos_srom_offsets)); ARRAY_SIZE(exynos_srom_offsets));
return 0; return 0;
} }
#endif #endif
......
drivers/memory/samsung/exynos5422-dmc.c
View file @ d7c6dbc0
...@@ -1398,7 +1398,7 @@ static int exynos5_dmc_probe(struct platform_device *pdev) ...@@ -1398,7 +1398,7 @@ static int exynos5_dmc_probe(struct platform_device *pdev)
return PTR_ERR(dmc->base_drexi1); return PTR_ERR(dmc->base_drexi1);
dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
"samsung,syscon-clk"); "samsung,syscon-clk");
if (IS_ERR(dmc->clk_regmap)) if (IS_ERR(dmc->clk_regmap))
return PTR_ERR(dmc->clk_regmap); return PTR_ERR(dmc->clk_regmap);
...@@ -1477,7 +1477,6 @@ static int exynos5_dmc_probe(struct platform_device *pdev) ...@@ -1477,7 +1477,6 @@ static int exynos5_dmc_probe(struct platform_device *pdev)
exynos5_dmc_df_profile.polling_ms = 500; exynos5_dmc_df_profile.polling_ms = 500;
} }
dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
DEVFREQ_GOV_SIMPLE_ONDEMAND, DEVFREQ_GOV_SIMPLE_ONDEMAND,
&dmc->gov_data); &dmc->gov_data);
......
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