Commit d82689bd authored by Oliver Upton's avatar Oliver Upton Committed by Marc Zyngier

KVM: selftests: Align with kernel's GIC definitions

There are a few subtle incongruencies between the GIC definitions used
by the kernel and selftests. Furthermore, the selftests header blends
implementation detail (e.g. default priority) with the architectural
definitions.

This is all rather annoying, since bulk imports of the kernel header
is not possible. Move selftests-specific definitions out of the
offending header and realign tests on the canonical definitions for
things like sysregs. Finally, haul in a fresh copy of the gicv3 header
to enable a forthcoming ITS selftest.
Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240422200158.2606761-14-oliver.upton@linux.devSigned-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 481c9ee8
...@@ -152,7 +152,7 @@ static void reset_stats(void) ...@@ -152,7 +152,7 @@ static void reset_stats(void)
static uint64_t gic_read_ap1r0(void) static uint64_t gic_read_ap1r0(void)
{ {
uint64_t reg = read_sysreg_s(SYS_ICV_AP1R0_EL1); uint64_t reg = read_sysreg_s(SYS_ICC_AP1R0_EL1);
dsb(sy); dsb(sy);
return reg; return reg;
...@@ -160,7 +160,7 @@ static uint64_t gic_read_ap1r0(void) ...@@ -160,7 +160,7 @@ static uint64_t gic_read_ap1r0(void)
static void gic_write_ap1r0(uint64_t val) static void gic_write_ap1r0(uint64_t val)
{ {
write_sysreg_s(val, SYS_ICV_AP1R0_EL1); write_sysreg_s(val, SYS_ICC_AP1R0_EL1);
isb(); isb();
} }
......
...@@ -9,9 +9,20 @@ ...@@ -9,9 +9,20 @@
#include "processor.h" #include "processor.h"
#include "delay.h" #include "delay.h"
#include "gic.h"
#include "gic_v3.h" #include "gic_v3.h"
#include "gic_private.h" #include "gic_private.h"
#define GICV3_MAX_CPUS 512
#define GICD_INT_DEF_PRI 0xa0
#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
(GICD_INT_DEF_PRI << 16) |\
(GICD_INT_DEF_PRI << 8) |\
GICD_INT_DEF_PRI)
#define ICC_PMR_DEF_PRIO 0xf0
struct gicv3_data { struct gicv3_data {
void *dist_base; void *dist_base;
void *redist_base[GICV3_MAX_CPUS]; void *redist_base[GICV3_MAX_CPUS];
...@@ -320,7 +331,7 @@ static void gicv3_cpu_init(unsigned int cpu, void *redist_base) ...@@ -320,7 +331,7 @@ static void gicv3_cpu_init(unsigned int cpu, void *redist_base)
write_sysreg_s(ICC_PMR_DEF_PRIO, SYS_ICC_PMR_EL1); write_sysreg_s(ICC_PMR_DEF_PRIO, SYS_ICC_PMR_EL1);
/* Enable non-secure Group-1 interrupts */ /* Enable non-secure Group-1 interrupts */
write_sysreg_s(ICC_IGRPEN1_EL1_ENABLE, SYS_ICC_GRPEN1_EL1); write_sysreg_s(ICC_IGRPEN1_EL1_MASK, SYS_ICC_IGRPEN1_EL1);
gicv3_data.redist_base[cpu] = redist_base_cpu; gicv3_data.redist_base[cpu] = redist_base_cpu;
} }
......
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