Commit d90a53d6 authored by Prike Liang's avatar Prike Liang Committed by Alex Deucher

drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry (v2)

The new amdgpu_gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.

v2: squash in warning fix (Alex)
Signed-off-by: default avatarPrike Liang <Prike.Liang@amd.com>
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4cd078dc
......@@ -819,3 +819,23 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
}
return amdgpu_num_kcq;
}
/* amdgpu_gfx_state_change_set - Handle gfx power state change set
* @adev: amdgpu_device pointer
* @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)
*
*/
void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
{
mutex_lock(&adev->pm.mutex);
if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->gfx_state_change_set)
((adev)->powerplay.pp_funcs->gfx_state_change_set(
(adev)->powerplay.pp_handle, state));
mutex_unlock(&adev->pm.mutex);
}
......@@ -47,6 +47,12 @@ enum gfx_pipe_priority {
AMDGPU_GFX_PIPE_PRIO_MAX
};
/* Argument for PPSMC_MSG_GpuChangeState */
enum gfx_change_state {
sGpuChangeState_D0Entry = 1,
sGpuChangeState_D3Entry,
};
#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
......@@ -394,4 +400,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
#endif
......@@ -285,6 +285,7 @@ struct amd_pm_funcs {
int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
int (*smu_i2c_bus_access)(void *handle, bool acquire);
int (*gfx_state_change_set)(void *handle, uint32_t state);
/* export to DC */
u32 (*get_sclk)(void *handle, bool low);
u32 (*get_mclk)(void *handle, bool low);
......
......@@ -366,6 +366,7 @@ struct pp_hwmgr_func {
int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
bool disable);
ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
};
struct pp_table_func {
......
......@@ -83,7 +83,8 @@
#define PPSMC_MSG_SetSoftMaxVcn 0x34
#define PPSMC_MSG_PowerGateMmHub 0x35
#define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36
#define PPSMC_Message_Count 0x37
#define PPSMC_MSG_GpuChangeState 0x37
#define PPSMC_Message_Count 0x42
typedef uint16_t PPSMC_Result;
typedef int PPSMC_Msg;
......
......@@ -1629,6 +1629,24 @@ static ssize_t pp_get_gpu_metrics(void *handle, void **table)
return size;
}
static int pp_gfx_state_change_set(void *handle, uint32_t state)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
pr_info_ratelimited("%s was not implemented.\n", __func__);
return -EINVAL;
}
mutex_lock(&hwmgr->smu_lock);
hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
mutex_unlock(&hwmgr->smu_lock);
return 0;
}
static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
......@@ -1691,4 +1709,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
.set_df_cstate = pp_set_df_cstate,
.set_xgmi_pstate = pp_set_xgmi_pstate,
.get_gpu_metrics = pp_get_gpu_metrics,
.gfx_state_change_set = pp_gfx_state_change_set,
};
......@@ -1439,6 +1439,13 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
return 0;
}
static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
{
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
return 0;
}
static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
.backend_init = smu10_hwmgr_backend_init,
.backend_fini = smu10_hwmgr_backend_fini,
......@@ -1485,6 +1492,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
.set_power_profile_mode = smu10_set_power_profile_mode,
.asic_reset = smu10_asic_reset,
.set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
.gfx_state_change = smu10_gfx_state_change,
};
int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
......
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