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Commit d9621fa0 authored by Anton Altaparmakov's avatar Anton Altaparmakov
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Merge cantab.net:/home/src/bklinux-2.6 

into cantab.net:/home/src/ntfs-2.6-devel
parents af81e654 cb91f479
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Showing with 402 additions and 198 deletions
arch/h8300/kernel/vmlinux.lds.S
View file @ d9621fa0
#define VMLINUX_SYMBOL(_sym_) _##_sym_
#include <asm-generic/vmlinux.lds.h>
#include <asm/thread_info.h>
#include <linux/config.h>
/* target memory map */
#ifdef CONFIG_H8300H_GENERIC
#ifdef CONFIG_ROMKERNEL
#include "../platform/h8300h/generic/rom.ld"
#endif
#ifdef CONFIG_RAMKERNEL
#include "../platform/h8300h/generic/ram.ld"
#endif
#define ROMTOP 0x000000
#define ROMSIZE 0x200000
#define RAMTOP 0x200000
#define RAMSIZE 0x200000
#endif
#ifdef CONFIG_H8300H_AKI3068NET
#ifdef CONFIG_ROMKERNEL
#include "../platform/h8300h/aki3068net/rom.ld"
#endif
#ifdef CONFIG_RAMKERNEL
#include "../platform/h8300h/aki3068net/ram.ld"
#endif
#define ROMTOP 0x000000
#define ROMSIZE 0x080000
#define RAMTOP 0x400000
#define RAMSIZE 0x200000
#endif
#ifdef CONFIG_H8300H_H8MAX
#ifdef CONFIG_ROMKERNEL
#include "../platform/h8300h/h8max/rom.ld"
#endif
#ifdef CONFIG_RAMKERNEL
#include "../platform/h8300h/h8max/ram.ld"
#endif
#define ROMTOP 0x000000
#define ROMSIZE 0x080000
#define RAMTOP 0x400000
#define RAMSIZE 0x200000
#endif
#ifdef CONFIG_H8300H_SIM
#ifdef CONFIG_ROMKERNEL
#include "../platform/h8300h/generic/rom.ld"
#endif
#ifdef CONFIG_RAMKERNEL
#include "../platform/h8300h/generic/ram.ld"
#endif
#define ROMTOP 0x000000
#define ROMSIZE 0x200000
#define RAMTOP 0x200000
#define RAMSIZE 0x200000
#endif
#ifdef CONFIG_H8S_SIM
#ifdef CONFIG_ROMKERNEL
#include "../platform/h8s/generic/rom.ld"
#endif
#ifdef CONFIG_RAMKERNEL
#include "../platform/h8s/generic/ram.ld"
#endif
#define ROMTOP 0x000000
#define ROMSIZE 0x200000
#define RAMTOP 0x200000
#define RAMSIZE 0x200000
#endif
#ifdef CONFIG_H8S_EDOSK2674
#ifdef CONFIG_ROMKERNEL
#include "../platform/h8s/edosk2674/rom.ld"
#endif
#ifdef CONFIG_RAMKERNEL
#include "../platform/h8s/edosk2674/ram.ld"
#endif
#define ROMTOP 0x000000
#define ROMSIZE 0x400000
#define RAMTOP 0x400000
#define RAMSIZE 0x800000
#endif
#if defined(CONFIG_H8300H_SIM) || defined(CONFIG_H8S_SIM)
......@@ -66,68 +54,45 @@ _jiffies = _jiffies_64 + 4;
SECTIONS
{
#if defined(CONFIG_ROMKERNEL)
. = ROMTOP;
.vectors :
{
__vector = . ;
*(.vectors*)
} > vector
#endif
#if defined(CONFIG_RAMKERNEL)
.bootvec :
}
#else
. = RAMTOP;
.bootvec :
{
*(.bootvec)
} > ram
}
#endif
.text :
{
#if defined(CONFIG_ROMKERNEL)
*(.int_redirect)
*(.int_redirect)
#endif
__stext = . ;
*(.text)
SCHED_TEXT
. = ALIGN(0x4) ;
*(.exit.text)
*(.text.*)
. = ALIGN(0x4) ;
*(.exitcall.exit)
. = ALIGN(0x4) ;
*(.kstrtab)
. = ALIGN(0x4) ;
*(.rodata*)
LOCK_TEXT
__etext = . ;
. = ALIGN(16); /* Exception table */
___start___ex_table = .;
*(__ex_table)
___stop___ex_table = .;
___start___ksymtab = .; /* Kernel symbol table */
*(__ksymtab)
___stop___ksymtab = .;
___start___ksymtab_gpl = .; /* Kernel symbol table: GPL-only symbols */
*(__ksymtab_gpl)
___stop___ksymtab_gpl = .;
___start___kcrctab = .; /* Kernel symbol table: Normal symbols */
*(__kcrctab)
___stop___kcrctab = .;
___start___kcrctab_gpl = .; /* Kernel symbol table: GPL-only symbols */
*(__kcrctab_gpl)
___stop___kcrctab_gpl = .;
*(__ksymtab_strings) /* Kernel symbol table: strings */
. = ALIGN(0x4) ;
__etext = . ;
RODATA
#if defined(CONFIG_ROMKERNEL)
} > rom
SECURITY_INIT
#endif
#if defined(CONFIG_RAMKERNEL)
} > ram
ROEND = .;
#if defined(CONFIG_ROMKERNEL)
. = RAMTOP;
.data : AT(ROEND)
#else
.data :
#endif
.data : AT( ADDR(.text)+SIZEOF(.text))
{
__sdata = . ;
___data_start = . ;
......@@ -162,6 +127,8 @@ SECTIONS
___con_initcall_start = .;
*(.con_initcall.init)
___con_initcall_end = .;
*(.exit.text)
*(.exit.data)
. = ALIGN(4);
___initramfs_start = .;
*(.init.ramfs)
......@@ -169,13 +136,13 @@ SECTIONS
. = ALIGN(0x4) ;
___init_end = .;
__edata = . ;
} > ram
}
#if defined(CONFIG_RAMKERNEL)
SECURITY_INIT
#endif
__begin_data = LOADADDR(.data) ;
#if defined(CONFIG_ROMKERNEL)
.erom :
{
__erom = . ;
} > erom
__erom = LOADADDR(.data) + SIZEOF(.data) ;
#endif
.bss :
{
......@@ -188,15 +155,19 @@ SECTIONS
__ebss = . ;
__end = . ;
__ramstart = .;
} > ram
}
/DISCARD/ : {
*(.exitcall.exit)
}
.romfs :
{
*(.romfs*)
} > ram
}
. = RAMTOP+RAMSIZE;
.dummy :
{
COMMAND_START = . - 0x200 ;
__ramend = . ;
} > eram
}
}
arch/h8300/platform/h8300h/aki3068net/ram.ld deleted 100644 → 0
View file @ af81e654
/* AE-3068 (aka. aki3068net) RAM */
OUTPUT_ARCH(h8300h)
ENTRY("__start")
MEMORY
{
ram : ORIGIN = 0x400000, LENGTH = 0x600000-0x400000
eram : ORIGIN = 0x600000, LENGTH = 0
iram : ORIGIN = 0xffbf20, LENGTH = 0x4000
}
arch/h8300/platform/h8300h/generic/ram.ld deleted 100644 → 0
View file @ af81e654
/* Generic RAM */
OUTPUT_ARCH(h8300h)
ENTRY("__start")
MEMORY
{
ram : ORIGIN = 0x400000, LENGTH = 0x200000
eram : ORIGIN = 0x600000, LENGTH = 0
iram : ORIGIN = 0xffbf20, LENGTH = 0x4000
}
arch/h8300/platform/h8300h/generic/rom.ld deleted 100644 → 0
View file @ af81e654
OUTPUT_ARCH(h8300h)
ENTRY("__start")
MEMORY
{
vector : ORIGIN = 0x000000, LENGTH = 0x000100
rom : ORIGIN = 0x000100, LENGTH = 0x200000-0x000100
erom : ORIGIN = 0x200000, LENGTH = 0
ram : ORIGIN = 0x200000, LENGTH = 0x400000
eram : ORIGIN = 0x600000, LENGTH = 0
}
arch/h8300/platform/h8300h/h8max/ram.ld deleted 100644 → 0
View file @ af81e654
/* H8MAX RAM */
OUTPUT_ARCH(h8300h)
ENTRY("__start")
MEMORY
{
ram : ORIGIN = 0x400000, LENGTH = 0x600000-0x400000
eram : ORIGIN = 0x600000, LENGTH = 0
iram : ORIGIN = 0xfffd20, LENGTH = 0x100
}
arch/h8300/platform/h8s/edosk2674/crt0_rom.S
View file @ d9621fa0
......@@ -181,7 +181,7 @@ __command_line:
.long __start
.long __start
vector = 2
.rept 126-1
.rept 126
.long _interrupt_redirect_table+vector*4
vector = vector + 1
.endr
arch/h8300/platform/h8s/edosk2674/ram.ld deleted 100644 → 0
View file @ af81e654
/* EDOSK-2674R RAM */
OUTPUT_ARCH(h8300s)
ENTRY("__start")
MEMORY
{
ram : ORIGIN = 0x400000, LENGTH = 0xc00000-0x400000
eram : ORIGIN = 0xc00000, LENGTH = 0
}
arch/h8300/platform/h8s/edosk2674/rom.ld deleted 100644 → 0
View file @ af81e654
OUTPUT_ARCH(h8300s)
ENTRY("__start")
MEMORY
{
vector : ORIGIN = 0x000000, LENGTH = 0x000200
rom : ORIGIN = 0x000200, LENGTH = 0x100000-0x000200
erom : ORIGIN = 0x100000, LENGTH = 0
ram : ORIGIN = 0x400000, LENGTH = 0xc00000-0x400000
eram : ORIGIN = 0xc00000, LENGTH = 0
}
arch/h8300/platform/h8s/generic/ram.ld deleted 100644 → 0
View file @ af81e654
OUTPUT_ARCH(h8300s)
ENTRY("__start")
MEMORY
{
ram : ORIGIN = 0x400000, LENGTH = 0x200000
eram : ORIGIN = 0x600000, LENGTH = 0
}
arch/h8300/platform/h8s/generic/rom.ld deleted 100644 → 0
View file @ af81e654
OUTPUT_ARCH(h8300s)
ENTRY("__start")
MEMORY
{
vector : ORIGIN = 0x000000, LENGTH = 0x000200
rom : ORIGIN = 0x000200, LENGTH = 0x200000-0x000200
erom : ORIGIN = 0x200000, LENGTH = 0
ram : ORIGIN = 0x200000, LENGTH = 0x400000
eram : ORIGIN = 0x600000, LENGTH = 0
}
arch/m68knommu/platform/5272/CANCam/crt0_ram.S 0 → 100644
View file @ d9621fa0
/*****************************************************************************/
/*
* crt0_ram.S -- startup code for Feith CANCan board.
*
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
* (C) Copyright 2000, Lineo (www.lineo.com).
*/
/*****************************************************************************/
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/*****************************************************************************/
/*
* Feith ColdFire CANCam, chip select and memory setup.
*/
#define MEM_BASE 0x00000000 /* Memory base at address 0 */
#define VBR_BASE MEM_BASE /* Vector address */
#define MEM_SIZE 0x04000000 /* Memory size 64Mb */
/*****************************************************************************/
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
/*****************************************************************************/
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
_rambase:
.long 0
_ramvec:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
/*****************************************************************************/
.text
/*
* This is the codes first entry point. This is where it all
* begins...
*/
_start:
nop /* Filler */
move.w #0x2700, %sr /* No interrupts */
/*
* Setup VBR here, otherwise buserror remap will not work.
* if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
*
* bkr@cut.de 19990306
*
* Note: this is because dBUG points VBR to ROM, making vectors read
* only, so the bus trap can't be changed. (RS)
*/
move.l #VBR_BASE, %a7 /* Note VBR can't be read */
movec %a7, %VBR
move.l %a7, _ramvec /* Set up vector addr */
move.l %a7, _rambase /* Set up base RAM addr */
/*
* Set memory size.
*/
move.l #MEM_SIZE, %a0
move.l %a0, %d0 /* Mem end addr is in a0 */
move.l %d0, %sp /* Set up initial stack ptr */
move.l %d0, _ramend /* Set end ram addr */
/*
* Enable CPU internal cache.
*/
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0x80000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
#ifdef CONFIG_ROMFS_FS
/*
* Move ROM filesystem above bss :-)
*/
lea.l _sbss, %a0 /* Get start of bss */
lea.l _ebss, %a1 /* Set up destination */
move.l %a0, %a2 /* Copy of bss start */
move.l 8(%a0), %d0 /* Get size of ROMFS */
addq.l #8, %d0 /* Allow for rounding */
and.l #0xfffffffc, %d0 /* Whole words */
add.l %d0, %a0 /* Copy from end */
add.l %d0, %a1 /* Copy from end */
move.l %a1, _ramstart /* Set start of ram */
_copy_romfs:
move.l -(%a0), %d0 /* Copy dword */
move.l %d0, -(%a1)
cmp.l %a0, %a2 /* Check if at end */
bne _copy_romfs
#else /* CONFIG_ROMFS_FS */
lea.l _ebss, %a1
move.l %a1, _ramstart
#endif /* CONFIG_ROMFS_FS */
/*
* Zero out the bss region.
*/
lea.l _sbss, %a0 /* Get start of bss */
lea.l _ebss, %a1 /* Get end of bss */
clr.l %d0 /* Set value */
_clear_bss:
move.l %d0, (%a0)+ /* Clear each word */
cmp.l %a0, %a1 /* Check if at end */
bne _clear_bss
/*
* Load the current thread pointer and stack.
*/
lea init_thread_union, %a0
lea 0x2000(%a0), %sp
/*
* Assember start up done, start code proper.
*/
jsr start_kernel /* Start Linux kernel */
_exit:
jmp _exit /* Should never get here */
/*****************************************************************************/
arch/m68knommu/platform/527x/M5275EVB/crt0_ram.S 0 → 100644
View file @ d9621fa0
/*****************************************************************************/
/*
* crt0_ram.S -- startup code for MCF527x ColdFire based Freescale boards.
*
* (C) Copyright 2003-2004, Greg Ungerer (gerg@snapgear.com).
*/
/*****************************************************************************/
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/*****************************************************************************/
/*
* Freescale M5275EVB ColdFire eval board, chip select and memory setup.
*/
#define MEM_BASE 0x00000000 /* Memory base at address 0 */
#define VBR_BASE MEM_BASE /* Vector address */
#if defined(CONFIG_RAM4MB)
#define MEM_SIZE 0x00400000 /* Memory size 4Mb */
#elif defined(CONFIG_RAM8MB)
#define MEM_SIZE 0x00800000 /* Memory size 8Mb */
#else
#define MEM_SIZE 0x01000000 /* Memory size 16Mb */
#endif
/*****************************************************************************/
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
/*****************************************************************************/
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
_rambase:
.long 0
_ramvec:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
/*****************************************************************************/
.text
/*
* This is the codes first entry point. This is where it all
* begins...
*/
_start:
nop /* Filler */
move.w #0x2700, %sr /* No interrupts */
/*
* Setup VBR here, otherwise buserror remap will not work.
* if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
*
* bkr@cut.de 19990306
*
* Note: this is because dBUG points VBR to ROM, making vectors read
* only, so the bus trap can't be changed. (RS)
*/
move.l #VBR_BASE, %a7 /* Note VBR can't be read */
movec %a7, %VBR
move.l %a7, _ramvec /* Set up vector addr */
move.l %a7, _rambase /* Set up base RAM addr */
/*
* Set memory size.
*/
move.l #MEM_SIZE, %a0
move.l %a0, %d0 /* Mem end addr is in a0 */
move.l %d0, %sp /* Set up initial stack ptr */
move.l %d0, _ramend /* Set end ram addr */
/*
* Enable CPU internal cache.
*/
move.l #0x01400000, %d0
movec %d0, %CACR /* Invalidate cache */
nop
move.l #0x0000c000, %d0 /* Set SDRAM cached only */
movec %d0, %ACR0
move.l #0x00000000, %d0 /* No other regions cached */
movec %d0, %ACR1
move.l #0x80400100, %d0 /* Configure cache */
movec %d0, %CACR /* Enable cache */
nop
#ifdef CONFIG_ROMFS_FS
/*
* Move ROM filesystem above bss :-)
*/
lea.l _sbss, %a0 /* Get start of bss */
lea.l _ebss, %a1 /* Set up destination */
move.l %a0, %a2 /* Copy of bss start */
move.l 8(%a0), %d0 /* Get size of ROMFS */
addq.l #8, %d0 /* Allow for rounding */
and.l #0xfffffffc, %d0 /* Whole words */
add.l %d0, %a0 /* Copy from end */
add.l %d0, %a1 /* Copy from end */
move.l %a1, _ramstart /* Set start of ram */
_copy_romfs:
move.l -(%a0), %d0 /* Copy dword */
move.l %d0, -(%a1)
cmp.l %a0, %a2 /* Check if at end */
bne _copy_romfs
#else /* CONFIG_ROMFS_FS */
lea.l _ebss, %a1
move.l %a1, _ramstart
#endif /* CONFIG_ROMFS_FS */
/*
* Zero out the bss region.
*/
lea.l _sbss, %a0 /* Get start of bss */
lea.l _ebss, %a1 /* Get end of bss */
clr.l %d0 /* Set value */
_clear_bss:
move.l %d0, (%a0)+ /* Clear each word */
cmp.l %a0, %a1 /* Check if at end */
bne _clear_bss
/*
* Load the current thread pointer and stack.
*/
lea init_thread_union, %a0
lea 0x2000(%a0), %sp
/*
* Assember start up done, start code proper.
*/
jsr start_kernel /* Start Linux kernel */
_exit:
jmp _exit /* Should never get here */
/*****************************************************************************/
arch/m68knommu/platform/5282/MOTOROLA/crt0_ram.S → arch/m68knommu/platform/528x/M5282EVB/crt0_ram.S
View file @ d9621fa0
/*****************************************************************************/
/*
* crt0_ram.S -- startup code for MCF5282 ColdFire based MOTOROLA boards.
* crt0_ram.S -- startup code for M5282EVB ColdFire based MOTOROLA boards.
*
* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com).
*/
......@@ -18,7 +18,7 @@
/*****************************************************************************/
/*
* Motorola M5282C3 ColdFire eval board, chip select and memory setup.
* Motorola M5282EVB ColdFire eval board, chip select and memory setup.
*/
#define MEM_BASE 0x00000000 /* Memory base at address 0 */
......
arch/m68knommu/platform/5282/Makefile → arch/m68knommu/platform/528x/Makefile
View file @ d9621fa0
......@@ -16,6 +16,6 @@ ifdef CONFIG_FULLDEBUG
AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
obj-y := config.o pit.o
obj-y := config.o
extra-y := $(BOARD)/crt0_$(MODEL).o
arch/m68knommu/platform/5282/config.c → arch/m68knommu/platform/528x/config.c
View file @ d9621fa0
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/5282/config.c
* linux/arch/m68knommu/platform/528x/config.c
*
* Sub-architcture dependant initialization code for the Motorola
* 5282 CPU.
* 5280 and 5282 CPUs.
*
* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
......
arch/m68knommu/platform/5407/config.c
View file @ d9621fa0
......@@ -23,7 +23,6 @@
#include <asm/mcftimer.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
#include <asm/delay.h>
/***************************************************************************/
......
drivers/net/fec.h
View file @ d9621fa0
/****************************************************************************/
/*
* fec.h -- Fast Ethernet Controller for Motorola ColdFire 5272
* and 5282..
* fec.h -- Fast Ethernet Controller for Motorola ColdFire 5270,
5271, 5272, 5274, 5275, 5280 and 5282.
*
* (C) Copyright 2000-2003, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000-2001, Lineo (www.lineo.com)
......@@ -13,7 +13,7 @@
#define FEC_H
/****************************************************************************/
#ifdef CONFIG_M5282
#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
/*
* Just figures, Motorola would have to change the offsets for
* registers in the same peripheral device on different models
......
include/asm-h8300/bitops.h
View file @ d9621fa0
......@@ -6,7 +6,6 @@
* Copyright 2002, Yoshinori Sato
*/
#include <linux/kernel.h>
#include <linux/config.h>
#include <linux/compiler.h>
#include <asm/byteorder.h> /* swab32 */
......@@ -181,6 +180,8 @@ H8300_GEN_TEST_BITOP(test_and_change_bit,"bnot")
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
#define ffs(x) generic_ffs(x)
static __inline__ unsigned long __ffs(unsigned long word)
{
unsigned long result;
......@@ -195,9 +196,6 @@ static __inline__ unsigned long __ffs(unsigned long word)
return result;
}
#define ffs(x) generic_ffs(x)
#define fls(x) generic_fls(x)
static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
{
unsigned long *p = (unsigned long *)(((unsigned long)addr + (offset >> 3)) & ~3);
......@@ -407,4 +405,6 @@ static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned lon
#endif /* __KERNEL__ */
#define fls(x) generic_fls(x)
#endif /* _H8300_BITOPS_H */
include/asm-h8300/delay.h
View file @ d9621fa0
......@@ -11,11 +11,10 @@
extern __inline__ void __delay(unsigned long loops)
{
__asm__ __volatile__ ("mov.l %0,er0\n\t"
"1:\n\t"
"dec.l #1,er0\n\t"
__asm__ __volatile__ ("1:\n\t"
"dec.l #1,%0\n\t"
"bne 1b"
::"r" (loops):"er0");
:"=r" (loops):"0"(loops));
}
/*
......
include/asm-h8300/system.h
View file @ d9621fa0
......@@ -2,7 +2,6 @@
#define _H8300_SYSTEM_H
#include <linux/config.h> /* get configuration macros */
#include <linux/kernel.h>
#include <linux/linkage.h>
#define prepare_to_switch() do { } while(0)
......@@ -119,7 +118,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
__asm__ __volatile__
("mov.b %2,%0\n\t"
"mov.b %1,%2"
: "=&r" (tmp) : "r" (x), "m" (*__xg(ptr)) : "er0","memory");
: "=&r" (tmp) : "r" (x), "m" (*__xg(ptr)) : "memory");
break;
case 2:
__asm__ __volatile__
......
include/asm-m68knommu/m5282sim.h → include/asm-m68knommu/m528xsim.h
View file @ d9621fa0
/****************************************************************************/
/*
* m5282sim.h -- ColdFire 5282 System Integration Module support.
* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
*
* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m5282sim_h
#define m5282sim_h
#ifndef m528xsim_h
#define m528xsim_h
/****************************************************************************/
#include <linux/config.h>
/*
* Define the 5282 SIM register set addresses.
* Define the 5280/5282 SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
......@@ -28,8 +28,9 @@
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
/****************************************************************************/
#endif /* m5282sim_h */
#endif /* m528xsim_h */
include/linux/bitops.h
View file @ d9621fa0
......@@ -42,7 +42,7 @@ static inline int generic_ffs(int x)
* fls: find last bit set.
*/
extern __inline__ int generic_fls(int x)
static __inline__ int generic_fls(int x)
{
int r = 32;
......@@ -71,7 +71,7 @@ extern __inline__ int generic_fls(int x)
return r;
}
extern __inline__ int get_bitmask_order(unsigned int count)
static __inline__ int get_bitmask_order(unsigned int count)
{
int order;
......
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