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Commit d99c1c2a authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: msm8992: Modernize the DTS style 

Following changes have been made:

- remove name, compatible and msm-id
- wrap clocks in clocks{}
- order nodes by name and by address
- clock_gcc -> gcc
- msmgpio -> tlmm
- retire msm8992-pins.dtsi
- add some of the missing pins
- make comments C-style
- make apcs a mailbox
Signed-off-by: default avatarKonrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200625182118.131476-2-konradybcio@gmail.comSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 551969ad
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arch/arm64/boot/dts/qcom/msm8992-pins.dtsi deleted 100644 → 0
View file @ 551969ad
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*/
&msmgpio {
blsp1_uart2_default: blsp1_uart2_default {
pinmux {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
};
/* 0-3 for sdc1 4-6 for sdc2 */
/* Order of pins */
/* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */
/* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */
sdc1_clk_on: clk-on {
pinconf {
pins = "sdc1_clk";
bias-disable = <0>; /* No pull */
drive-strength = <16>; /* 16mA */
};
};
sdc1_clk_off: clk-off {
pinconf {
pins = "sdc1_clk";
bias-disable = <0>; /* No pull */
drive-strength = <2>; /* 2mA */
};
};
sdc1_cmd_on: cmd-on {
pinconf {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <8>;
};
};
sdc1_cmd_off: cmd-off {
pinconf {
pins = "sdc1_cmd";
bias-pull-up = <0x3>; /* same as 3.10 ?? */
drive-strength = <2>; /* 2mA */
};
};
sdc1_data_on: data-on {
pinconf {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>; /* 8mA */
};
};
sdc1_data_off: data-off {
pinconf {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
};
sdc1_rclk_on: rclk-on {
bias-pull-down; /* pull down */
};
sdc1_rclk_off: rclk-off {
bias-pull-down; /* pull down */
};
};
arch/arm64/boot/dts/qcom/msm8992.dtsi
View file @ d99c1c2a
......@@ -6,10 +6,6 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ {
model = "Qualcomm Technologies, Inc. MSM 8992";
compatible = "qcom,msm8992";
// msm-id needed by bootloader for selecting correct blob
qcom,msm-id = <251 0>, <252 0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
......@@ -40,35 +36,35 @@ L2_0: l2-cache {
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
vreg_vph_pwr: vreg-vph-pwr {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "vph-pwr";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
regulator-always-on;
smem_region: smem@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
};
};
sfpb_mutex: hwmutex {
......@@ -98,9 +94,10 @@ intc: interrupt-controller@f9000000 {
<0xf9002000 0x1000>;
};
apcs: syscon@f900d000 {
compatible = "syscon";
apcs: mailbox@f900d000 {
compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0xf900d000 0x2000>;
#mbox-cells = <1>;
};
timer@f9020000 {
......@@ -161,40 +158,6 @@ frame@f9028000 {
};
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
clock-names = "core", "iface";
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP1_AHB_CLK>;
};
clock_gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
sdhci1: mmc@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
......@@ -204,8 +167,8 @@ sdhci1: mmc@f9824900 {
<GIC_SPI 138 IRQ_TYPE_NONE>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>,
<&clock_gcc GCC_SDCC1_AHB_CLK>;
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
......@@ -220,32 +183,141 @@ sdhci1: mmc@f9824900 {
status = "okay";
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
status = "disabled";
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
rpm_msg_ram: memory@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
sfpb_mutex_regs: syscon@fd484000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "syscon";
reg = <0xfd484000 0x400>;
};
};
memory {
device_type = "memory";
reg = <0 0 0 0>; // bootloader will update
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
blsp1_uart2_default: blsp1-uart2-default {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
smem_region: smem@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
blsp1_uart2_sleep: blsp1-uart2-sleep {
function = "gpio";
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
sdc1_clk_on: clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <6>;
};
sdc1_clk_off: clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
sdc1_cmd_on: cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <6>;
};
sdc1_cmd_off: cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc1_data_on: data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <6>;
};
sdc1_data_off: data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sdc1_rclk_on: rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
};
sdc1_rclk_off: rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
};
i2c2_default: i2c2-default {
function = "blsp_i2c2";
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c2_sleep: i2c2-sleep {
function = "gpio";
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c6_default: i2c6-default {
function = "blsp_i2c6";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
i2c6_sleep: i2c6-sleep {
function = "gpio";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
};
};
......@@ -264,6 +336,24 @@ rpm_requests: rpm-requests {
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
vreg_vph_pwr: vreg-vph-pwr {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "vph-pwr";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
};
#include "msm8992-pins.dtsi"
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