Commit da9a73b7 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Lucas De Marchi

drm/xe/xe2hpg: Add Wa_15016589081

Wa_15016589081 applies to xe2_hpg renderCS

V2(Gustavo)
  - rename bit macro
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240904101333.2049655-1-tejas.upadhyay@intel.comSigned-off-by: default avatarNirmoy Das <nirmoy.das@intel.com>
(cherry picked from commit 9db969b36b2fbca13ad4088aff725ebd5e8142f5)
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 70b4ab54
......@@ -105,6 +105,7 @@
#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
#define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6)
#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
#define TBIMR_FAST_CLIP REG_BIT(5)
......
......@@ -733,6 +733,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
DIS_PARTIAL_AUTOSTRIP |
DIS_AUTOSTRIP))
},
{ XE_RTP_NAME("15016589081"),
XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
},
{}
};
......
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