Commit dad4cc58 authored by David S. Miller's avatar David S. Miller

[SPARC64]: Rework all EBUS DMA support.

- Add EBUS DMA layer so the same code does not need to
be debugged/duplicated several times.
- Convert Parport/Floppy/CS4231 to use new EBUS DMA layer.
parent 25757a5a
...@@ -8,7 +8,7 @@ EXTRA_AFLAGS := -ansi ...@@ -8,7 +8,7 @@ EXTRA_AFLAGS := -ansi
EXTRA_TARGETS := head.o init_task.o EXTRA_TARGETS := head.o init_task.o
export-objs := sparc64_ksyms.o export-objs := sparc64_ksyms.o ebus.o
obj-y := process.o setup.o cpu.o idprom.o \ obj-y := process.o setup.o cpu.o idprom.o \
traps.o devices.o auxio.o \ traps.o devices.o auxio.o \
irq.o ptrace.o time.o sys_sparc.o signal.o \ irq.o ptrace.o time.o sys_sparc.o signal.o \
......
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
*/ */
#include <linux/config.h> #include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/init.h> #include <linux/init.h>
...@@ -20,6 +21,220 @@ ...@@ -20,6 +21,220 @@
#include <asm/bpp.h> #include <asm/bpp.h>
#include <asm/irq.h> #include <asm/irq.h>
/* EBUS dma library. */
#define EBDMA_CSR 0x00UL /* Control/Status */
#define EBDMA_ADDR 0x04UL /* DMA Address */
#define EBDMA_COUNT 0x08UL /* DMA Count */
#define EBDMA_CSR_INT_PEND 0x00000001
#define EBDMA_CSR_ERR_PEND 0x00000002
#define EBDMA_CSR_DRAIN 0x00000004
#define EBDMA_CSR_INT_EN 0x00000010
#define EBDMA_CSR_RESET 0x00000080
#define EBDMA_CSR_WRITE 0x00000100
#define EBDMA_CSR_EN_DMA 0x00000200
#define EBDMA_CSR_CYC_PEND 0x00000400
#define EBDMA_CSR_DIAG_RD_DONE 0x00000800
#define EBDMA_CSR_DIAG_WR_DONE 0x00001000
#define EBDMA_CSR_EN_CNT 0x00002000
#define EBDMA_CSR_TC 0x00004000
#define EBDMA_CSR_DIS_CSR_DRN 0x00010000
#define EBDMA_CSR_BURST_SZ_MASK 0x000c0000
#define EBDMA_CSR_BURST_SZ_1 0x00080000
#define EBDMA_CSR_BURST_SZ_4 0x00000000
#define EBDMA_CSR_BURST_SZ_8 0x00040000
#define EBDMA_CSR_BURST_SZ_16 0x000c0000
#define EBDMA_CSR_DIAG_EN 0x00100000
#define EBDMA_CSR_DIS_ERR_PEND 0x00400000
#define EBDMA_CSR_TCI_DIS 0x00800000
#define EBDMA_CSR_EN_NEXT 0x01000000
#define EBDMA_CSR_DMA_ON 0x02000000
#define EBDMA_CSR_A_LOADED 0x04000000
#define EBDMA_CSR_NA_LOADED 0x08000000
#define EBDMA_CSR_DEV_ID_MASK 0xf0000000
#define EBUS_DMA_RESET_TIMEOUT 10000
static void __ebus_dma_reset(struct ebus_dma_info *p)
{
int i;
u32 val = 0;
writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR);
for (i = EBUS_DMA_RESET_TIMEOUT; i > 0; i--) {
val = readl(p->regs + EBDMA_CSR);
if (!(val & (EBDMA_CSR_DRAIN | EBDMA_CSR_CYC_PEND)))
break;
udelay(10);
}
}
static void ebus_dma_irq(int irq, void *dev_id, struct pt_regs *regs)
{
struct ebus_dma_info *p = dev_id;
unsigned long flags;
u32 csr;
spin_lock_irqsave(&p->lock, flags);
csr = readl(p->regs + EBDMA_CSR);
writel(csr, p->regs + EBDMA_CSR);
spin_unlock_irqrestore(&p->lock, flags);
if (csr & EBDMA_CSR_ERR_PEND) {
printk(KERN_CRIT "ebus_dma(%s): DMA error!\n", p->name);
p->callback(p, EBUS_DMA_EVENT_ERROR, p->client_cookie);
} else if (csr & EBDMA_CSR_INT_PEND) {
p->callback(p,
(csr & EBDMA_CSR_TC) ?
EBUS_DMA_EVENT_DMA : EBUS_DMA_EVENT_DEVICE,
p->client_cookie);
}
}
int ebus_dma_register(struct ebus_dma_info *p)
{
if (!p->regs)
return -EINVAL;
if (p->flags & ~(EBUS_DMA_FLAG_USE_EBDMA_HANDLER))
return -EINVAL;
if ((p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) && !p->callback)
return -EINVAL;
if (!strlen(p->name))
return -EINVAL;
__ebus_dma_reset(p);
return 0;
}
EXPORT_SYMBOL(ebus_dma_register);
int ebus_dma_irq_enable(struct ebus_dma_info *p, int on)
{
unsigned long flags;
u32 csr;
if (on) {
if (p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) {
if (request_irq(p->irq, ebus_dma_irq, SA_SHIRQ, p->name, p))
return -EBUSY;
}
spin_lock_irqsave(&p->lock, flags);
csr = readl(p->regs + EBDMA_CSR);
csr |= EBDMA_CSR_INT_EN;
writel(csr, p->regs + EBDMA_CSR);
spin_unlock_irqrestore(&p->lock, flags);
} else {
spin_lock_irqsave(&p->lock, flags);
csr = readl(p->regs + EBDMA_CSR);
csr &= ~EBDMA_CSR_INT_EN;
writel(csr, p->regs + EBDMA_CSR);
spin_unlock_irqrestore(&p->lock, flags);
if (p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) {
free_irq(p->irq, p);
}
}
return 0;
}
EXPORT_SYMBOL(ebus_dma_irq_enable);
void ebus_dma_unregister(struct ebus_dma_info *p)
{
unsigned long flags;
u32 csr;
int irq_on = 0;
spin_lock_irqsave(&p->lock, flags);
csr = readl(p->regs + EBDMA_CSR);
if (csr & EBDMA_CSR_INT_EN) {
csr &= ~EBDMA_CSR_INT_EN;
writel(csr, p->regs + EBDMA_CSR);
irq_on = 1;
}
spin_unlock_irqrestore(&p->lock, flags);
if (irq_on)
free_irq(p->irq, p);
}
EXPORT_SYMBOL(ebus_dma_unregister);
int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr, size_t len)
{
unsigned long flags;
u32 csr;
int err;
if (len >= (1 << 24))
return -EINVAL;
spin_lock_irqsave(&p->lock, flags);
csr = readl(p->regs + EBDMA_CSR);
err = -EINVAL;
if (!(csr & EBDMA_CSR_EN_DMA))
goto out;
err = -EBUSY;
if (csr & EBDMA_CSR_NA_LOADED)
goto out;
writel(len, p->regs + EBDMA_COUNT);
writel(bus_addr, p->regs + EBDMA_ADDR);
err = 0;
out:
spin_unlock_irqrestore(&p->lock, flags);
return err;
}
EXPORT_SYMBOL(ebus_dma_request);
void ebus_dma_prepare(struct ebus_dma_info *p, int write)
{
unsigned long flags;
spin_lock_irqsave(&p->lock, flags);
__ebus_dma_reset(p);
writel(EBDMA_CSR_INT_EN |
((write) ? EBDMA_CSR_WRITE : 0) |
EBDMA_CSR_EN_CNT |
EBDMA_CSR_BURST_SZ_16 |
EBDMA_CSR_EN_NEXT, p->regs + EBDMA_CSR);
spin_unlock_irqrestore(&p->lock, flags);
}
EXPORT_SYMBOL(ebus_dma_prepare);
unsigned int ebus_dma_residue(struct ebus_dma_info *p)
{
return readl(p->regs + EBDMA_COUNT);
}
EXPORT_SYMBOL(ebus_dma_residue);
unsigned int ebus_dma_addr(struct ebus_dma_info *p)
{
return readl(p->regs + EBDMA_ADDR);
}
EXPORT_SYMBOL(ebus_dma_addr);
void ebus_dma_enable(struct ebus_dma_info *p, int on)
{
unsigned long flags;
u32 csr;
spin_lock_irqsave(&p->lock, flags);
csr = readl(p->regs + EBDMA_CSR);
if (on)
csr |= EBDMA_CSR_EN_DMA;
else
csr &= ~EBDMA_CSR_EN_DMA;
writel(csr, p->regs + EBDMA_CSR);
spin_unlock_irqrestore(&p->lock, flags);
}
EXPORT_SYMBOL(ebus_dma_enable);
struct linux_ebus *ebus_chain = 0; struct linux_ebus *ebus_chain = 0;
#ifdef CONFIG_SUN_AUXIO #ifdef CONFIG_SUN_AUXIO
......
...@@ -51,38 +51,34 @@ struct linux_ebus { ...@@ -51,38 +51,34 @@ struct linux_ebus {
struct linux_prom_ebus_intmask ebus_intmask; struct linux_prom_ebus_intmask ebus_intmask;
}; };
struct linux_ebus_dma { struct ebus_dma_info {
unsigned int dcsr; spinlock_t lock;
unsigned int dacr; unsigned long regs;
unsigned int dbcr;
unsigned int flags;
#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
/* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
* set.
*/
void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
void *client_cookie;
unsigned int irq;
#define EBUS_DMA_EVENT_ERROR 1
#define EBUS_DMA_EVENT_DMA 2
#define EBUS_DMA_EVENT_DEVICE 4
unsigned char name[64];
}; };
#define EBUS_DCSR_INT_PEND 0x00000001 extern int ebus_dma_register(struct ebus_dma_info *p);
#define EBUS_DCSR_ERR_PEND 0x00000002 extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
#define EBUS_DCSR_DRAIN 0x00000004 extern void ebus_dma_unregister(struct ebus_dma_info *p);
#define EBUS_DCSR_INT_EN 0x00000010 extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
#define EBUS_DCSR_RESET 0x00000080 size_t len);
#define EBUS_DCSR_WRITE 0x00000100 extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
#define EBUS_DCSR_EN_DMA 0x00000200 extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
#define EBUS_DCSR_CYC_PEND 0x00000400 extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
#define EBUS_DCSR_EN_CNT 0x00002000
#define EBUS_DCSR_TC 0x00004000
#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
#define EBUS_DCSR_BURST_SZ_1 0x00080000
#define EBUS_DCSR_BURST_SZ_4 0x00000000
#define EBUS_DCSR_BURST_SZ_8 0x00040000
#define EBUS_DCSR_BURST_SZ_16 0x000c0000
#define EBUS_DCSR_DIAG_EN 0x00100000
#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
#define EBUS_DCSR_TCI_DIS 0x00800000
#define EBUS_DCSR_EN_NEXT 0x01000000
#define EBUS_DCSR_DMA_ON 0x02000000
#define EBUS_DCSR_A_LOADED 0x04000000
#define EBUS_DCSR_NA_LOADED 0x08000000
#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
extern struct linux_ebus *ebus_chain; extern struct linux_ebus *ebus_chain;
......
...@@ -264,7 +264,7 @@ static int sun_fd_eject(int drive) ...@@ -264,7 +264,7 @@ static int sun_fd_eject(int drive)
#include <asm/isa.h> #include <asm/isa.h>
#include <asm/ns87303.h> #include <asm/ns87303.h>
static struct linux_ebus_dma *sun_pci_fd_ebus_dma; static struct ebus_dma_info sun_pci_fd_ebus_dma;
static struct pci_dev *sun_pci_ebus_dev; static struct pci_dev *sun_pci_ebus_dev;
static int sun_pci_broken_drive = -1; static int sun_pci_broken_drive = -1;
...@@ -330,26 +330,12 @@ static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port) ...@@ -330,26 +330,12 @@ static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port)
} }
#endif /* PCI_FDC_SWAP_DRIVES */ #endif /* PCI_FDC_SWAP_DRIVES */
static void sun_pci_fd_reset_dma(void)
{
unsigned int dcsr;
writel(EBUS_DCSR_RESET, &sun_pci_fd_ebus_dma->dcsr);
udelay(1);
dcsr = EBUS_DCSR_BURST_SZ_16 | EBUS_DCSR_TCI_DIS |
EBUS_DCSR_EN_CNT;
writel(dcsr, (unsigned long)&sun_pci_fd_ebus_dma->dcsr);
}
static void sun_pci_fd_enable_dma(void) static void sun_pci_fd_enable_dma(void)
{ {
unsigned int dcsr; if ((NULL == sun_pci_dma_pending.buf) ||
(0 == sun_pci_dma_pending.len) ||
if((NULL == sun_pci_dma_pending.buf) || (0 == sun_pci_dma_pending.direction))
(0 == sun_pci_dma_pending.len) || BUG();
(0 == sun_pci_dma_pending.direction)) {
goto enable; /* TODO: BUG() */
}
sun_pci_dma_current.buf = sun_pci_dma_pending.buf; sun_pci_dma_current.buf = sun_pci_dma_pending.buf;
sun_pci_dma_current.len = sun_pci_dma_pending.len; sun_pci_dma_current.len = sun_pci_dma_pending.len;
...@@ -361,36 +347,22 @@ static void sun_pci_fd_enable_dma(void) ...@@ -361,36 +347,22 @@ static void sun_pci_fd_enable_dma(void)
sun_pci_dma_pending.addr = -1U; sun_pci_dma_pending.addr = -1U;
sun_pci_dma_current.addr = sun_pci_dma_current.addr =
pci_map_single( sun_pci_ebus_dev, pci_map_single(sun_pci_ebus_dev,
sun_pci_dma_current.buf, sun_pci_dma_current.buf,
sun_pci_dma_current.len, sun_pci_dma_current.len,
sun_pci_dma_current.direction); sun_pci_dma_current.direction);
writel(sun_pci_dma_current.addr, &sun_pci_fd_ebus_dma->dacr);
if (ebus_dma_request(&sun_pci_fd_ebus_dma,
sun_pci_dma_current.addr,
sun_pci_dma_current.len))
BUG();
enable: ebus_dma_enable(&sun_pci_fd_ebus_dma, 1);
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
dcsr |= EBUS_DCSR_EN_DMA;
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
} }
static void sun_pci_fd_disable_dma(void) static void sun_pci_fd_disable_dma(void)
{ {
unsigned int dcsr; ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
if (dcsr & EBUS_DCSR_EN_DMA) {
while (dcsr & EBUS_DCSR_DRAIN) {
udelay(1);
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
}
dcsr &= ~(EBUS_DCSR_EN_DMA);
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
if (dcsr & EBUS_DCSR_ERR_PEND) {
sun_pci_fd_reset_dma();
dcsr &= ~(EBUS_DCSR_ERR_PEND);
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
}
}
if (sun_pci_dma_current.addr != -1U) if (sun_pci_dma_current.addr != -1U)
pci_unmap_single(sun_pci_ebus_dev, pci_unmap_single(sun_pci_ebus_dev,
sun_pci_dma_current.addr, sun_pci_dma_current.addr,
...@@ -401,33 +373,12 @@ static void sun_pci_fd_disable_dma(void) ...@@ -401,33 +373,12 @@ static void sun_pci_fd_disable_dma(void)
static void sun_pci_fd_set_dma_mode(int mode) static void sun_pci_fd_set_dma_mode(int mode)
{ {
unsigned int dcsr; ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
if (readl(&sun_pci_fd_ebus_dma->dbcr)) {
sun_pci_fd_reset_dma();
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
}
dcsr |= EBUS_DCSR_EN_CNT | EBUS_DCSR_TC;
/*
* For EBus WRITE means to system memory, which is
* READ for us.
*/
if (mode == DMA_MODE_WRITE) {
dcsr &= ~(EBUS_DCSR_WRITE);
sun_pci_dma_pending.direction = PCI_DMA_TODEVICE;
} else {
dcsr |= EBUS_DCSR_WRITE;
sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE;
}
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
} }
static void sun_pci_fd_set_dma_count(int length) static void sun_pci_fd_set_dma_count(int length)
{ {
sun_pci_dma_pending.len = length; sun_pci_dma_pending.len = length;
writel(length, &sun_pci_fd_ebus_dma->dbcr);
} }
static void sun_pci_fd_set_dma_addr(char *buffer) static void sun_pci_fd_set_dma_addr(char *buffer)
...@@ -437,51 +388,28 @@ static void sun_pci_fd_set_dma_addr(char *buffer) ...@@ -437,51 +388,28 @@ static void sun_pci_fd_set_dma_addr(char *buffer)
static unsigned int sun_pci_get_dma_residue(void) static unsigned int sun_pci_get_dma_residue(void)
{ {
unsigned int dcsr, res; return ebus_dma_residue(&sun_pci_fd_ebus_dma);
res = readl(&sun_pci_fd_ebus_dma->dbcr);
if (res != 0) {
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
sun_pci_fd_reset_dma();
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
}
return res;
} }
static void sun_pci_fd_enable_irq(void) static void sun_pci_fd_enable_irq(void)
{ {
unsigned int dcsr; ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 1);
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
dcsr |= EBUS_DCSR_INT_EN;
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
} }
static void sun_pci_fd_disable_irq(void) static void sun_pci_fd_disable_irq(void)
{ {
unsigned int dcsr; ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 0);
dcsr = readl(&sun_pci_fd_ebus_dma->dcsr);
dcsr &= ~(EBUS_DCSR_INT_EN);
writel(dcsr, &sun_pci_fd_ebus_dma->dcsr);
} }
static int sun_pci_fd_request_irq(void) static int sun_pci_fd_request_irq(void)
{ {
int err; /* Done by enable/disable irq */
err = request_irq(FLOPPY_IRQ, floppy_interrupt, SA_SHIRQ,
"floppy", sun_fdc);
if (err)
return -1;
sun_pci_fd_enable_irq();
return 0; return 0;
} }
static void sun_pci_fd_free_irq(void) static void sun_pci_fd_free_irq(void)
{ {
sun_pci_fd_disable_irq(); /* Done by enable/disable irq */
free_irq(FLOPPY_IRQ, sun_fdc);
} }
static int sun_pci_fd_eject(int drive) static int sun_pci_fd_eject(int drive)
...@@ -489,6 +417,10 @@ static int sun_pci_fd_eject(int drive) ...@@ -489,6 +417,10 @@ static int sun_pci_fd_eject(int drive)
return -EINVAL; return -EINVAL;
} }
void sun_pci_fd_dma_callback(struct ebus_dma_info *p, int event, void *cookie)
{
floppy_interrupt(0, NULL, NULL);
}
/* /*
* Floppy probing, we'd like to use /dev/fd0 for a single Floppy on PCI, * Floppy probing, we'd like to use /dev/fd0 for a single Floppy on PCI,
...@@ -724,6 +656,7 @@ static unsigned long __init sun_floppy_init(void) ...@@ -724,6 +656,7 @@ static unsigned long __init sun_floppy_init(void)
if(!strncmp(state, "disabled", 8)) if(!strncmp(state, "disabled", 8))
return 0; return 0;
/* XXX ioremap */
sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start; sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start;
FLOPPY_IRQ = edev->irqs[0]; FLOPPY_IRQ = edev->irqs[0];
...@@ -735,9 +668,18 @@ static unsigned long __init sun_floppy_init(void) ...@@ -735,9 +668,18 @@ static unsigned long __init sun_floppy_init(void)
sun_pci_ebus_dev = ebus->self; sun_pci_ebus_dev = ebus->self;
sun_pci_fd_ebus_dma = (struct linux_ebus_dma *) spin_lock_init(&sun_pci_fd_ebus_dma.lock);
edev->resource[1].start; /* XXX ioremap */
sun_pci_fd_reset_dma(); sun_pci_fd_ebus_dma.regs = edev->resource[1].start;
if (!sun_pci_fd_ebus_dma.regs)
return 0;
sun_pci_fd_ebus_dma.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
sun_pci_fd_ebus_dma.callback = sun_pci_fd_dma_callback;
sun_pci_fd_ebus_dma.client_cookie = NULL;
sun_pci_fd_ebus_dma.irq = FLOPPY_IRQ;
strcpy(sun_pci_fd_ebus_dma.name, "floppy");
if (ebus_dma_register(&sun_pci_fd_ebus_dma))
return 0;
sun_fdops.fd_inb = sun_pci_fd_inb; sun_fdops.fd_inb = sun_pci_fd_inb;
sun_fdops.fd_outb = sun_pci_fd_outb; sun_fdops.fd_outb = sun_pci_fd_outb;
......
...@@ -13,91 +13,50 @@ ...@@ -13,91 +13,50 @@
#define PARPORT_PC_MAX_PORTS PARPORT_MAX #define PARPORT_PC_MAX_PORTS PARPORT_MAX
static struct linux_ebus_dma *sparc_ebus_dmas[PARPORT_PC_MAX_PORTS]; static struct sparc_ebus_info {
struct ebus_dma_info info;
unsigned int addr;
unsigned int count;
} sparc_ebus_dmas[PARPORT_PC_MAX_PORTS];
static __inline__ void static __inline__ void enable_dma(unsigned int dmanr)
reset_dma(unsigned int dmanr)
{ {
unsigned int dcsr; if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
sparc_ebus_dmas[dmanr].addr,
sparc_ebus_dmas[dmanr].count))
BUG();
writel(EBUS_DCSR_RESET, &sparc_ebus_dmas[dmanr]->dcsr); ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
udelay(1);
dcsr = EBUS_DCSR_BURST_SZ_16 | EBUS_DCSR_TCI_DIS |
EBUS_DCSR_EN_CNT | EBUS_DCSR_INT_EN;
writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr);
} }
static __inline__ void static __inline__ void disable_dma(unsigned int dmanr)
enable_dma(unsigned int dmanr)
{ {
unsigned int dcsr; ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 0);
dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr);
dcsr |= EBUS_DCSR_EN_DMA;
writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr);
} }
static __inline__ void static __inline__ void clear_dma_ff(unsigned int dmanr)
disable_dma(unsigned int dmanr)
{
unsigned int dcsr;
dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr);
if (dcsr & EBUS_DCSR_EN_DMA) {
while (dcsr & EBUS_DCSR_DRAIN) {
udelay(1);
dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr);
}
dcsr &= ~(EBUS_DCSR_EN_DMA);
writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr);
dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr);
if (dcsr & EBUS_DCSR_ERR_PEND)
reset_dma(dmanr);
}
}
static __inline__ void
clear_dma_ff(unsigned int dmanr)
{ {
/* nothing */ /* nothing */
} }
static __inline__ void static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
set_dma_mode(unsigned int dmanr, char mode)
{ {
unsigned int dcsr; ebus_dma_prepare(&sparc_ebus_dmas[dmanr].info, (mode != DMA_MODE_WRITE));
dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr);
dcsr |= EBUS_DCSR_EN_CNT | EBUS_DCSR_TC;
if (mode == DMA_MODE_WRITE)
dcsr &= ~(EBUS_DCSR_WRITE);
else
dcsr |= EBUS_DCSR_WRITE;
writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr);
} }
static __inline__ void static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int addr)
set_dma_addr(unsigned int dmanr, unsigned int addr)
{ {
writel(addr, &sparc_ebus_dmas[dmanr]->dacr); sparc_ebus_dmas[dmanr].addr = addr;
} }
static __inline__ void static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
set_dma_count(unsigned int dmanr, unsigned int count)
{ {
writel(count, &sparc_ebus_dmas[dmanr]->dbcr); sparc_ebus_dmas[dmanr].count = count;
} }
static __inline__ int static __inline__ unsigned int get_dma_residue(unsigned int dmanr)
get_dma_residue(unsigned int dmanr)
{ {
int res; return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
res = readl(&sparc_ebus_dmas[dmanr]->dbcr);
if (res != 0)
reset_dma(dmanr);
return res;
} }
static int ebus_ecpp_p(struct linux_ebus_device *edev) static int ebus_ecpp_p(struct linux_ebus_device *edev)
...@@ -171,10 +130,19 @@ static int parport_pc_find_nonpci_ports (int autoirq, int autodma) ...@@ -171,10 +130,19 @@ static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
unsigned long base = edev->resource[0].start; unsigned long base = edev->resource[0].start;
unsigned long config = edev->resource[1].start; unsigned long config = edev->resource[1].start;
sparc_ebus_dmas[count] = spin_lock_init(&sparc_ebus_dmas[count].info);
(struct linux_ebus_dma *) sparc_ebus_dmas[count].info.regs =
edev->resource[2].start; edev->resource[2].start;
reset_dma(count); if (!sparc_ebus_dmas[count].info.regs)
continue;
sparc_ebus_dmas[count].info.flags = 0;
sparc_ebus_dmas[count].info.callback = NULL;
sparc_ebus_dmas[count].info.client_cookie = NULL;
sparc_ebus_dmas[count].info.irq = 0xdeadbeef;
strcpy(sparc_ebus_dmas[count].info.name, "parport");
if (ebus_dma_register(&sparc_ebus_dmas[count].info))
continue;
ebus_dma_irq_enable(&sparc_ebus_dmas[count].info, 1);
/* Configure IRQ to Push Pull, Level Low */ /* Configure IRQ to Push Pull, Level Low */
/* Enable ECP, set bit 2 of the CTR first */ /* Enable ECP, set bit 2 of the CTR first */
......
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