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Commit dc732f50 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: S5P64x0: Modify platform data for pl330 driver 

With the 'struct dma_pl330_peri' removed, the platfrom data for dma
driver can be simplified to a simple list of peripheral request ids.

Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 66fdb29d
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Showing with 65 additions and 162 deletions
arch/arm/mach-s5p64x0/dma.c
View file @ dc732f50
...@@ -38,176 +38,74 @@ ...@@ -38,176 +38,74 @@
static u64 dma_dmamask = DMA_BIT_MASK(32); static u64 dma_dmamask = DMA_BIT_MASK(32);
struct dma_pl330_peri s5p6440_pdma_peri[22] = { u8 s5p6440_pdma_peri[] = {
{ DMACH_UART0_RX,
.peri_id = (u8)DMACH_UART0_RX, DMACH_UART0_TX,
.rqtype = DEVTOMEM, DMACH_UART1_RX,
}, { DMACH_UART1_TX,
.peri_id = (u8)DMACH_UART0_TX, DMACH_UART2_RX,
.rqtype = MEMTODEV, DMACH_UART2_TX,
}, { DMACH_UART3_RX,
.peri_id = (u8)DMACH_UART1_RX, DMACH_UART3_TX,
.rqtype = DEVTOMEM, DMACH_MAX,
}, { DMACH_MAX,
.peri_id = (u8)DMACH_UART1_TX, DMACH_PCM0_TX,
.rqtype = MEMTODEV, DMACH_PCM0_RX,
}, { DMACH_I2S0_TX,
.peri_id = (u8)DMACH_UART2_RX, DMACH_I2S0_RX,
.rqtype = DEVTOMEM, DMACH_SPI0_TX,
}, { DMACH_SPI0_RX,
.peri_id = (u8)DMACH_UART2_TX, DMACH_MAX,
.rqtype = MEMTODEV, DMACH_MAX,
}, { DMACH_MAX,
.peri_id = (u8)DMACH_UART3_RX, DMACH_MAX,
.rqtype = DEVTOMEM, DMACH_SPI1_TX,
}, { DMACH_SPI1_RX,
.peri_id = (u8)DMACH_UART3_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = DMACH_MAX,
}, {
.peri_id = DMACH_MAX,
}, {
.peri_id = (u8)DMACH_PCM0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_PCM0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_SPI1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI1_RX,
.rqtype = DEVTOMEM,
},
}; };
struct dma_pl330_platdata s5p6440_pdma_pdata = { struct dma_pl330_platdata s5p6440_pdma_pdata = {
.nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
.peri = s5p6440_pdma_peri, .peri_id = s5p6440_pdma_peri,
}; };
struct dma_pl330_peri s5p6450_pdma_peri[32] = { u8 s5p6450_pdma_peri[] = {
{ DMACH_UART0_RX,
.peri_id = (u8)DMACH_UART0_RX, DMACH_UART0_TX,
.rqtype = DEVTOMEM, DMACH_UART1_RX,
}, { DMACH_UART1_TX,
.peri_id = (u8)DMACH_UART0_TX, DMACH_UART2_RX,
.rqtype = MEMTODEV, DMACH_UART2_TX,
}, { DMACH_UART3_RX,
.peri_id = (u8)DMACH_UART1_RX, DMACH_UART3_TX,
.rqtype = DEVTOMEM, DMACH_UART4_RX,
}, { DMACH_UART4_TX,
.peri_id = (u8)DMACH_UART1_TX, DMACH_PCM0_TX,
.rqtype = MEMTODEV, DMACH_PCM0_RX,
}, { DMACH_I2S0_TX,
.peri_id = (u8)DMACH_UART2_RX, DMACH_I2S0_RX,
.rqtype = DEVTOMEM, DMACH_SPI0_TX,
}, { DMACH_SPI0_RX,
.peri_id = (u8)DMACH_UART2_TX, DMACH_PCM1_TX,
.rqtype = MEMTODEV, DMACH_PCM1_RX,
}, { DMACH_PCM2_TX,
.peri_id = (u8)DMACH_UART3_RX, DMACH_PCM2_RX,
.rqtype = DEVTOMEM, DMACH_SPI1_TX,
}, { DMACH_SPI1_RX,
.peri_id = (u8)DMACH_UART3_TX, DMACH_USI_TX,
.rqtype = MEMTODEV, DMACH_USI_RX,
}, { DMACH_MAX,
.peri_id = (u8)DMACH_UART4_RX, DMACH_I2S1_TX,
.rqtype = DEVTOMEM, DMACH_I2S1_RX,
}, { DMACH_I2S2_TX,
.peri_id = (u8)DMACH_UART4_TX, DMACH_I2S2_RX,
.rqtype = MEMTODEV, DMACH_PWM,
}, { DMACH_UART5_RX,
.peri_id = (u8)DMACH_PCM0_TX, DMACH_UART5_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_PCM0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI0_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI0_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_PCM1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_PCM1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_PCM2_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_PCM2_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_SPI1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_SPI1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_USI_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_USI_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_MAX,
}, {
.peri_id = (u8)DMACH_I2S1_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S1_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_I2S2_TX,
.rqtype = MEMTODEV,
}, {
.peri_id = (u8)DMACH_I2S2_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_PWM,
}, {
.peri_id = (u8)DMACH_UART5_RX,
.rqtype = DEVTOMEM,
}, {
.peri_id = (u8)DMACH_UART5_TX,
.rqtype = MEMTODEV,
},
}; };
struct dma_pl330_platdata s5p6450_pdma_pdata = { struct dma_pl330_platdata s5p6450_pdma_pdata = {
.nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
.peri = s5p6450_pdma_peri, .peri_id = s5p6450_pdma_peri,
}; };
struct amba_device s5p64x0_device_pdma = { struct amba_device s5p64x0_device_pdma = {
...@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = { ...@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = {
static int __init s5p64x0_dma_init(void) static int __init s5p64x0_dma_init(void)
{ {
if (soc_is_s5p6450()) if (soc_is_s5p6450()) {
dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
else } else {
dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
}
amba_device_register(&s5p64x0_device_pdma, &iomem_resource); amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
......
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