Commit ddcdb1b4 authored by David Daney's avatar David Daney Committed by Ralf Baechle

MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.

Signed-off-by: default avatarTomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: default avatarPaul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent babed555
...@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS]; ...@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ #define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
#define SMP_CALL_FUNCTION 0x2 #define SMP_CALL_FUNCTION 0x2
/* Octeon - Tell another core to flush its icache */
#define SMP_ICACHE_FLUSH 0x4
extern void asmlinkage smp_bootstrap(void); extern void asmlinkage smp_bootstrap(void);
......
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