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Commit de1af8d4 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Jason Cooper
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ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes 

Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 0cd3754a
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Showing with 140 additions and 138 deletions
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ de1af8d4
......@@ -45,6 +45,56 @@ soc {
controller = <&mbusc>;
interrupt-parent = <&mpic>;
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -200,50 +250,6 @@ spi1: spi@10680 {
status = "disabled";
};
devbus-bootcs@10400 {
compatible = "marvell,mvebu-devbus";
reg = <0x10400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0@10408 {
compatible = "marvell,mvebu-devbus";
reg = <0x10408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1@10410 {
compatible = "marvell,mvebu-devbus";
reg = <0x10410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2@10418 {
compatible = "marvell,mvebu-devbus";
reg = <0x10418 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3@10420 {
compatible = "marvell,mvebu-devbus";
reg = <0x10420 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/armada-xp-db.dts
View file @ de1af8d4
......@@ -31,7 +31,36 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
devbus-bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
internal-regs {
serial@12000 {
......@@ -160,34 +189,6 @@ pcie@10,0 {
};
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>;
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
};
};
};
arch/arm/boot/dts/armada-xp-gp.dts
View file @ de1af8d4
......@@ -40,7 +40,36 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
devbus-bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
internal-regs {
serial@12000 {
......@@ -126,35 +155,6 @@ spi-flash@0 {
};
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file @ de1af8d4
......@@ -28,7 +28,36 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
devbus-bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
internal-regs {
serial@12000 {
......@@ -148,40 +177,6 @@ usb@51000 {
status = "okay";
};
/* USB interface in the mini-PCIe connector */
usb@52000 {
status = "okay";
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
......
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