Commit deb125ab authored by Russell King's avatar Russell King

ARM: l2c: omap2: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 7eab0039
...@@ -213,20 +213,18 @@ static int __init omap_l2_cache_init(void) ...@@ -213,20 +213,18 @@ static int __init omap_l2_cache_init(void)
return -ENOMEM; return -ENOMEM;
/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
aux_ctrl = L310_AUX_CTRL_ASSOCIATIVITY_16 | aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR |
L310_AUX_CTRL_CACHE_REPLACE_RR |
L310_AUX_CTRL_NS_LOCKDOWN | L310_AUX_CTRL_NS_LOCKDOWN |
L310_AUX_CTRL_NS_INT_CTRL | L310_AUX_CTRL_NS_INT_CTRL |
L2C_AUX_CTRL_WAY_SIZE(3) |
L2C_AUX_CTRL_SHARED_OVERRIDE | L2C_AUX_CTRL_SHARED_OVERRIDE |
L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_DATA_PREFETCH |
L310_AUX_CTRL_INSTR_PREFETCH; L310_AUX_CTRL_INSTR_PREFETCH;
outer_cache.write_sec = omap4_l2c310_write_sec; outer_cache.write_sec = omap4_l2c310_write_sec;
if (of_have_populated_dt()) if (of_have_populated_dt())
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); l2x0_of_init(aux_ctrl, 0xc19fffff);
else else
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff);
return 0; return 0;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment