Commit e17dca2b authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Ulf Hansson

mmc: mmci: add ddrmode mask to variant data

This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.

Without this patch datactrl register is updated with incorrect ddrmode mask,
resulting in failures on Qualcomm SD Card Controller.
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Resolved conflict
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent ff783233
...@@ -59,6 +59,7 @@ static unsigned int fmax = 515633; ...@@ -59,6 +59,7 @@ static unsigned int fmax = 515633;
* is asserted (likewise for RX) * is asserted (likewise for RX)
* @sdio: variant supports SDIO * @sdio: variant supports SDIO
* @st_clkdiv: true if using a ST-specific clock divider algorithm * @st_clkdiv: true if using a ST-specific clock divider algorithm
* @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
* @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
* register * register
...@@ -74,6 +75,7 @@ struct variant_data { ...@@ -74,6 +75,7 @@ struct variant_data {
unsigned int datalength_bits; unsigned int datalength_bits;
unsigned int fifosize; unsigned int fifosize;
unsigned int fifohalfsize; unsigned int fifohalfsize;
unsigned int datactrl_mask_ddrmode;
bool sdio; bool sdio;
bool st_clkdiv; bool st_clkdiv;
bool blksz_datactrl16; bool blksz_datactrl16;
...@@ -152,6 +154,7 @@ static struct variant_data variant_ux500v2 = { ...@@ -152,6 +154,7 @@ static struct variant_data variant_ux500v2 = {
.fifohalfsize = 8 * 4, .fifohalfsize = 8 * 4,
.clkreg = MCI_CLK_ENABLE, .clkreg = MCI_CLK_ENABLE,
.clkreg_enable = MCI_ST_UX500_HWFCEN, .clkreg_enable = MCI_ST_UX500_HWFCEN,
.datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
.datalength_bits = 24, .datalength_bits = 24,
.sdio = true, .sdio = true,
.st_clkdiv = true, .st_clkdiv = true,
...@@ -772,7 +775,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) ...@@ -772,7 +775,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
datactrl |= MCI_ST_DPSM_DDRMODE; datactrl |= variant->datactrl_mask_ddrmode;
/* /*
* Attempt to use DMA operation mode, if this * Attempt to use DMA operation mode, if this
......
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