Commit e1a84d56 authored by Oded Gabbay's avatar Oded Gabbay

habanalabs: use registers name defines for ETR block

We have a single ETR block in the SOC, so use explicit register
name defines for initializing this block. This makes it more readable and
maintainable.
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: default avatarOmer Shpigelman <oshpigelman@habana.ai>
parent f05912d8
...@@ -377,33 +377,32 @@ static int goya_config_etr(struct hl_device *hdev, ...@@ -377,33 +377,32 @@ static int goya_config_etr(struct hl_device *hdev,
struct hl_debug_params *params) struct hl_debug_params *params)
{ {
struct hl_debug_params_etr *input; struct hl_debug_params_etr *input;
u64 base_reg = mmPSOC_ETR_BASE - CFG_BASE;
u32 val; u32 val;
int rc; int rc;
WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
val = RREG32(base_reg + 0x304); val = RREG32(mmPSOC_ETR_FFCR);
val |= 0x1000; val |= 0x1000;
WREG32(base_reg + 0x304, val); WREG32(mmPSOC_ETR_FFCR, val);
val |= 0x40; val |= 0x40;
WREG32(base_reg + 0x304, val); WREG32(mmPSOC_ETR_FFCR, val);
rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false); rc = goya_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
if (rc) { if (rc) {
dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
params->enable ? "enable" : "disable", rc); params->enable ? "enable" : "disable", rc);
return rc; return rc;
} }
rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true); rc = goya_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
if (rc) { if (rc) {
dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
params->enable ? "enable" : "disable", rc); params->enable ? "enable" : "disable", rc);
return rc; return rc;
} }
WREG32(base_reg + 0x20, 0); WREG32(mmPSOC_ETR_CTL, 0);
if (params->enable) { if (params->enable) {
input = params->input; input = params->input;
...@@ -423,25 +422,25 @@ static int goya_config_etr(struct hl_device *hdev, ...@@ -423,25 +422,25 @@ static int goya_config_etr(struct hl_device *hdev,
return -EINVAL; return -EINVAL;
} }
WREG32(base_reg + 0x34, 0x3FFC); WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
WREG32(base_reg + 0x4, input->buffer_size); WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
WREG32(base_reg + 0x28, input->sink_mode); WREG32(mmPSOC_ETR_MODE, input->sink_mode);
WREG32(base_reg + 0x110, 0x700); WREG32(mmPSOC_ETR_AXICTL, 0x700);
WREG32(base_reg + 0x118, WREG32(mmPSOC_ETR_DBALO,
lower_32_bits(input->buffer_address)); lower_32_bits(input->buffer_address));
WREG32(base_reg + 0x11C, WREG32(mmPSOC_ETR_DBAHI,
upper_32_bits(input->buffer_address)); upper_32_bits(input->buffer_address));
WREG32(base_reg + 0x304, 3); WREG32(mmPSOC_ETR_FFCR, 3);
WREG32(base_reg + 0x308, 0xA); WREG32(mmPSOC_ETR_PSCR, 0xA);
WREG32(base_reg + 0x20, 1); WREG32(mmPSOC_ETR_CTL, 1);
} else { } else {
WREG32(base_reg + 0x34, 0); WREG32(mmPSOC_ETR_BUFWM, 0);
WREG32(base_reg + 0x4, 0x400); WREG32(mmPSOC_ETR_RSZ, 0x400);
WREG32(base_reg + 0x118, 0); WREG32(mmPSOC_ETR_DBALO, 0);
WREG32(base_reg + 0x11C, 0); WREG32(mmPSOC_ETR_DBAHI, 0);
WREG32(base_reg + 0x308, 0); WREG32(mmPSOC_ETR_PSCR, 0);
WREG32(base_reg + 0x28, 0); WREG32(mmPSOC_ETR_MODE, 0);
WREG32(base_reg + 0x304, 0); WREG32(mmPSOC_ETR_FFCR, 0);
if (params->output_size >= sizeof(u64)) { if (params->output_size >= sizeof(u64)) {
u32 rwp, rwphi; u32 rwp, rwphi;
...@@ -451,8 +450,8 @@ static int goya_config_etr(struct hl_device *hdev, ...@@ -451,8 +450,8 @@ static int goya_config_etr(struct hl_device *hdev,
* the buffer is set in the RWP register (lower 32 * the buffer is set in the RWP register (lower 32
* bits), and in the RWPHI register (upper 8 bits). * bits), and in the RWPHI register (upper 8 bits).
*/ */
rwp = RREG32(base_reg + 0x18); rwp = RREG32(mmPSOC_ETR_RWP);
rwphi = RREG32(base_reg + 0x3c) & 0xff; rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
*(u64 *) params->output = ((u64) rwphi << 32) | rwp; *(u64 *) params->output = ((u64) rwphi << 32) | rwp;
} }
} }
......
...@@ -84,6 +84,7 @@ ...@@ -84,6 +84,7 @@
#include "tpc6_rtr_regs.h" #include "tpc6_rtr_regs.h"
#include "tpc7_nrtr_regs.h" #include "tpc7_nrtr_regs.h"
#include "tpc0_eml_cfg_regs.h" #include "tpc0_eml_cfg_regs.h"
#include "psoc_etr_regs.h"
#include "psoc_global_conf_masks.h" #include "psoc_global_conf_masks.h"
#include "dma_macro_masks.h" #include "dma_macro_masks.h"
......
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_PSOC_ETR_REGS_H_
#define ASIC_REG_PSOC_ETR_REGS_H_
/*
*****************************************
* PSOC_ETR (Prototype: ETR)
*****************************************
*/
#define mmPSOC_ETR_RSZ 0x2C43004
#define mmPSOC_ETR_STS 0x2C4300C
#define mmPSOC_ETR_RRD 0x2C43010
#define mmPSOC_ETR_RRP 0x2C43014
#define mmPSOC_ETR_RWP 0x2C43018
#define mmPSOC_ETR_TRG 0x2C4301C
#define mmPSOC_ETR_CTL 0x2C43020
#define mmPSOC_ETR_RWD 0x2C43024
#define mmPSOC_ETR_MODE 0x2C43028
#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C
#define mmPSOC_ETR_CBUFLEVEL 0x2C43030
#define mmPSOC_ETR_BUFWM 0x2C43034
#define mmPSOC_ETR_RRPHI 0x2C43038
#define mmPSOC_ETR_RWPHI 0x2C4303C
#define mmPSOC_ETR_AXICTL 0x2C43110
#define mmPSOC_ETR_DBALO 0x2C43118
#define mmPSOC_ETR_DBAHI 0x2C4311C
#define mmPSOC_ETR_FFSR 0x2C43300
#define mmPSOC_ETR_FFCR 0x2C43304
#define mmPSOC_ETR_PSCR 0x2C43308
#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0
#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8
#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC
#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0
#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4
#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8
#define mmPSOC_ETR_ITCTRL 0x2C43F00
#define mmPSOC_ETR_CLAIMSET 0x2C43FA0
#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4
#define mmPSOC_ETR_LAR 0x2C43FB0
#define mmPSOC_ETR_LSR 0x2C43FB4
#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8
#define mmPSOC_ETR_DEVID 0x2C43FC8
#define mmPSOC_ETR_DEVTYPE 0x2C43FCC
#define mmPSOC_ETR_PERIPHID4 0x2C43FD0
#define mmPSOC_ETR_PERIPHID5 0x2C43FD4
#define mmPSOC_ETR_PERIPHID6 0x2C43FD8
#define mmPSOC_ETR_PERIPHID7 0x2C43FDC
#define mmPSOC_ETR_PERIPHID0 0x2C43FE0
#define mmPSOC_ETR_PERIPHID1 0x2C43FE4
#define mmPSOC_ETR_PERIPHID2 0x2C43FE8
#define mmPSOC_ETR_PERIPHID3 0x2C43FEC
#define mmPSOC_ETR_COMPID0 0x2C43FF0
#define mmPSOC_ETR_COMPID1 0x2C43FF4
#define mmPSOC_ETR_COMPID2 0x2C43FF8
#define mmPSOC_ETR_COMPID3 0x2C43FFC
#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */
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