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Commit e36f561a authored by Linus Torvalds's avatar Linus Torvalds
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags 

* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags:
  Fix IRQ flag handling naming
  MIPS: Add missing #inclusions of <linux/irq.h>
  smc91x: Add missing #inclusion of <linux/irq.h>
  Drop a couple of unnecessary asm/system.h inclusions
  SH: Add missing consts to sys_execve() declaration
  Blackfin: Rename IRQ flags handling functions
  Blackfin: Add missing dep to asm/irqflags.h
  Blackfin: Rename DES PC2() symbol to avoid collision
  Blackfin: Split the BF532 BFIN_*_FIO_FLAG() functions to their own header
  Blackfin: Split PLL code from mach-specific cdef headers
parents 70ada779 df9ee292
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Showing with 2335 additions and 1847 deletions
arch/alpha/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
#ifndef __ALPHA_IRQFLAGS_H
#define __ALPHA_IRQFLAGS_H
#include <asm/system.h>
#define IPL_MIN 0
#define IPL_SW0 1
#define IPL_SW1 2
#define IPL_DEV0 3
#define IPL_DEV1 4
#define IPL_TIMER 5
#define IPL_PERF 6
#define IPL_POWERFAIL 6
#define IPL_MCHECK 7
#define IPL_MAX 7
#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
#undef IPL_MIN
#define IPL_MIN __min_ipl
extern int __min_ipl;
#endif
#define getipl() (rdps() & 7)
#define setipl(ipl) ((void) swpipl(ipl))
static inline unsigned long arch_local_save_flags(void)
{
return rdps();
}
static inline void arch_local_irq_disable(void)
{
setipl(IPL_MAX);
barrier();
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = swpipl(IPL_MAX);
barrier();
return flags;
}
static inline void arch_local_irq_enable(void)
{
barrier();
setipl(IPL_MIN);
}
static inline void arch_local_irq_restore(unsigned long flags)
{
barrier();
setipl(flags);
barrier();
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return flags == IPL_MAX;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(getipl());
}
#endif /* __ALPHA_IRQFLAGS_H */
arch/alpha/include/asm/system.h
View file @ e36f561a
......@@ -259,34 +259,6 @@ __CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
__CALL_PAL_W1(wrusp, unsigned long);
__CALL_PAL_W1(wrvptptr, unsigned long);
#define IPL_MIN 0
#define IPL_SW0 1
#define IPL_SW1 2
#define IPL_DEV0 3
#define IPL_DEV1 4
#define IPL_TIMER 5
#define IPL_PERF 6
#define IPL_POWERFAIL 6
#define IPL_MCHECK 7
#define IPL_MAX 7
#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
#undef IPL_MIN
#define IPL_MIN __min_ipl
extern int __min_ipl;
#endif
#define getipl() (rdps() & 7)
#define setipl(ipl) ((void) swpipl(ipl))
#define local_irq_disable() do { setipl(IPL_MAX); barrier(); } while(0)
#define local_irq_enable() do { barrier(); setipl(IPL_MIN); } while(0)
#define local_save_flags(flags) ((flags) = rdps())
#define local_irq_save(flags) do { (flags) = swpipl(IPL_MAX); barrier(); } while(0)
#define local_irq_restore(flags) do { barrier(); setipl(flags); barrier(); } while(0)
#define irqs_disabled() (getipl() == IPL_MAX)
/*
* TB routines..
*/
......
arch/arm/include/asm/irqflags.h
View file @ e36f561a
......@@ -10,66 +10,85 @@
*/
#if __LINUX_ARM_ARCH__ >= 6
#define raw_local_irq_save(x) \
({ \
__asm__ __volatile__( \
"mrs %0, cpsr @ local_irq_save\n" \
"cpsid i" \
: "=r" (x) : : "memory", "cc"); \
})
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
asm volatile(
" mrs %0, cpsr @ arch_local_irq_save\n"
" cpsid i"
: "=r" (flags) : : "memory", "cc");
return flags;
}
static inline void arch_local_irq_enable(void)
{
asm volatile(
" cpsie i @ arch_local_irq_enable"
:
:
: "memory", "cc");
}
static inline void arch_local_irq_disable(void)
{
asm volatile(
" cpsid i @ arch_local_irq_disable"
:
:
: "memory", "cc");
}
#define raw_local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
#define raw_local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
#else
/*
* Save the current interrupt enable state & disable IRQs
*/
#define raw_local_irq_save(x) \
({ \
unsigned long temp; \
(void) (&temp == &x); \
__asm__ __volatile__( \
"mrs %0, cpsr @ local_irq_save\n" \
" orr %1, %0, #128\n" \
" msr cpsr_c, %1" \
: "=r" (x), "=r" (temp) \
: \
: "memory", "cc"); \
})
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags, temp;
asm volatile(
" mrs %0, cpsr @ arch_local_irq_save\n"
" orr %1, %0, #128\n"
" msr cpsr_c, %1"
: "=r" (flags), "=r" (temp)
:
: "memory", "cc");
return flags;
}
/*
* Enable IRQs
*/
#define raw_local_irq_enable() \
({ \
unsigned long temp; \
__asm__ __volatile__( \
"mrs %0, cpsr @ local_irq_enable\n" \
" bic %0, %0, #128\n" \
" msr cpsr_c, %0" \
: "=r" (temp) \
: \
: "memory", "cc"); \
})
static inline void arch_local_irq_enable(void)
{
unsigned long temp;
asm volatile(
" mrs %0, cpsr @ arch_local_irq_enable\n"
" bic %0, %0, #128\n"
" msr cpsr_c, %0"
: "=r" (temp)
:
: "memory", "cc");
}
/*
* Disable IRQs
*/
#define raw_local_irq_disable() \
({ \
unsigned long temp; \
__asm__ __volatile__( \
"mrs %0, cpsr @ local_irq_disable\n" \
" orr %0, %0, #128\n" \
" msr cpsr_c, %0" \
: "=r" (temp) \
: \
: "memory", "cc"); \
})
static inline void arch_local_irq_disable(void)
{
unsigned long temp;
asm volatile(
" mrs %0, cpsr @ arch_local_irq_disable\n"
" orr %0, %0, #128\n"
" msr cpsr_c, %0"
: "=r" (temp)
:
: "memory", "cc");
}
/*
* Enable FIQs
......@@ -106,27 +125,31 @@
/*
* Save the current interrupt enable state.
*/
#define raw_local_save_flags(x) \
({ \
__asm__ __volatile__( \
"mrs %0, cpsr @ local_save_flags" \
: "=r" (x) : : "memory", "cc"); \
})
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile(
" mrs %0, cpsr @ local_save_flags"
: "=r" (flags) : : "memory", "cc");
return flags;
}
/*
* restore saved IRQ & FIQ state
*/
#define raw_local_irq_restore(x) \
__asm__ __volatile__( \
"msr cpsr_c, %0 @ local_irq_restore\n" \
: \
: "r" (x) \
: "memory", "cc")
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile(
" msr cpsr_c, %0 @ local_irq_restore"
:
: "r" (flags)
: "memory", "cc");
}
#define raw_irqs_disabled_flags(flags) \
({ \
(int)((flags) & PSR_I_BIT); \
})
static inline int arch_irqs_disabled_flags(unsigned long flags)
{
return flags & PSR_I_BIT;
}
#endif
#endif
arch/avr32/include/asm/irqflags.h
View file @ e36f561a
......@@ -8,16 +8,14 @@
#ifndef __ASM_AVR32_IRQFLAGS_H
#define __ASM_AVR32_IRQFLAGS_H
#include <linux/types.h>
#include <asm/sysreg.h>
static inline unsigned long __raw_local_save_flags(void)
static inline unsigned long arch_local_save_flags(void)
{
return sysreg_read(SR);
}
#define raw_local_save_flags(x) \
do { (x) = __raw_local_save_flags(); } while (0)
/*
* This will restore ALL status register flags, not only the interrupt
* mask flag.
......@@ -25,44 +23,39 @@ static inline unsigned long __raw_local_save_flags(void)
* The empty asm statement informs the compiler of this fact while
* also serving as a barrier.
*/
static inline void raw_local_irq_restore(unsigned long flags)
static inline void arch_local_irq_restore(unsigned long flags)
{
sysreg_write(SR, flags);
asm volatile("" : : : "memory", "cc");
}
static inline void raw_local_irq_disable(void)
static inline void arch_local_irq_disable(void)
{
asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET) : "memory");
}
static inline void raw_local_irq_enable(void)
static inline void arch_local_irq_enable(void)
{
asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET) : "memory");
}
static inline int raw_irqs_disabled_flags(unsigned long flags)
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & SYSREG_BIT(GM)) != 0;
}
static inline int raw_irqs_disabled(void)
static inline bool arch_irqs_disabled(void)
{
unsigned long flags = __raw_local_save_flags();
return raw_irqs_disabled_flags(flags);
return arch_irqs_disabled_flags(arch_local_save_flags());
}
static inline unsigned long __raw_local_irq_save(void)
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = __raw_local_save_flags();
unsigned long flags = arch_local_save_flags();
raw_local_irq_disable();
arch_local_irq_disable();
return flags;
}
#define raw_local_irq_save(flags) \
do { (flags) = __raw_local_irq_save(); } while (0)
#endif /* __ASM_AVR32_IRQFLAGS_H */
arch/blackfin/include/asm/ipipe.h
View file @ e36f561a
......@@ -49,7 +49,7 @@
#define prepare_arch_switch(next) \
do { \
ipipe_schedule_notify(current, next); \
local_irq_disable_hw(); \
hard_local_irq_disable(); \
} while (0)
#define task_hijacked(p) \
......@@ -57,7 +57,7 @@ do { \
int __x__ = __ipipe_root_domain_p; \
__clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
if (__x__) \
local_irq_enable_hw(); \
hard_local_irq_enable(); \
!__x__; \
})
......@@ -167,7 +167,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
#define __ipipe_run_isr(ipd, irq) \
do { \
if (!__ipipe_pipeline_head_p(ipd)) \
local_irq_enable_hw(); \
hard_local_irq_enable(); \
if (ipd == ipipe_root_domain) { \
if (unlikely(ipipe_virtual_irq_p(irq))) { \
irq_enter(); \
......@@ -183,7 +183,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
__ipipe_run_irqtail(); \
__set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
} \
local_irq_disable_hw(); \
hard_local_irq_disable(); \
} while (0)
#define __ipipe_syscall_watched_p(p, sc) \
......
arch/blackfin/include/asm/irqflags.h
View file @ e36f561a
......@@ -8,6 +8,8 @@
#ifndef __ASM_BFIN_IRQFLAGS_H__
#define __ASM_BFIN_IRQFLAGS_H__
#include <mach/blackfin.h>
#ifdef CONFIG_SMP
# include <asm/pda.h>
# include <asm/processor.h>
......@@ -31,54 +33,108 @@ static inline unsigned long bfin_cli(void)
return flags;
}
#ifdef CONFIG_IPIPE
#include <linux/compiler.h>
#include <linux/ipipe_base.h>
#include <linux/ipipe_trace.h>
#ifdef CONFIG_DEBUG_HWERR
# define bfin_no_irqs 0x3f
#else
# define bfin_no_irqs 0x1f
#endif
#define raw_local_irq_disable() \
do { \
ipipe_check_context(ipipe_root_domain); \
__ipipe_stall_root(); \
barrier(); \
} while (0)
/*****************************************************************************/
/*
* Hard, untraced CPU interrupt flag manipulation and access.
*/
static inline void __hard_local_irq_disable(void)
{
bfin_cli();
}
static inline void __hard_local_irq_enable(void)
{
bfin_sti(bfin_irq_flags);
}
static inline unsigned long hard_local_save_flags(void)
{
return bfin_read_IMASK();
}
#define raw_local_irq_enable() \
do { \
barrier(); \
ipipe_check_context(ipipe_root_domain); \
__ipipe_unstall_root(); \
} while (0)
static inline unsigned long __hard_local_irq_save(void)
{
unsigned long flags;
flags = bfin_cli();
#ifdef CONFIG_DEBUG_HWERR
bfin_sti(0x3f);
#endif
return flags;
}
static inline int hard_irqs_disabled_flags(unsigned long flags)
{
return (flags & ~0x3f) == 0;
}
static inline int hard_irqs_disabled(void)
{
unsigned long flags = hard_local_save_flags();
return hard_irqs_disabled_flags(flags);
}
static inline void __hard_local_irq_restore(unsigned long flags)
{
if (!hard_irqs_disabled_flags(flags))
__hard_local_irq_enable();
}
/*****************************************************************************/
/*
* Interrupt pipe handling.
*/
#ifdef CONFIG_IPIPE
#include <linux/compiler.h>
#include <linux/ipipe_base.h>
#include <linux/ipipe_trace.h>
/*
* Interrupt pipe interface to linux/irqflags.h.
*/
static inline void arch_local_irq_disable(void)
{
ipipe_check_context(ipipe_root_domain);
__ipipe_stall_root();
barrier();
}
#define raw_local_save_flags_ptr(x) \
do { \
*(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \
} while (0)
static inline void arch_local_irq_enable(void)
{
barrier();
ipipe_check_context(ipipe_root_domain);
__ipipe_unstall_root();
}
#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x))
static inline unsigned long arch_local_save_flags(void)
{
return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
}
#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs)
static inline int arch_irqs_disabled_flags(unsigned long flags)
{
return flags == bfin_no_irqs;
}
#define raw_local_irq_save_ptr(x) \
do { \
*(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \
barrier(); \
} while (0)
static inline void arch_local_irq_save_ptr(unsigned long *_flags)
{
x = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
barrier();
}
#define raw_local_irq_save(x) \
do { \
ipipe_check_context(ipipe_root_domain); \
raw_local_irq_save_ptr(&(x)); \
} while (0)
static inline unsigned long arch_local_irq_save(void)
{
ipipe_check_context(ipipe_root_domain);
return __hard_local_irq_save();
}
static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
{
/*
* Merge virtual and real interrupt mask bits into a single
......@@ -87,130 +143,79 @@ static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
return (real & ~(1 << 31)) | ((virt != 0) << 31);
}
static inline int raw_demangle_irq_bits(unsigned long *x)
static inline int arch_demangle_irq_bits(unsigned long *x)
{
int virt = (*x & (1 << 31)) != 0;
*x &= ~(1L << 31);
return virt;
}
static inline void local_irq_disable_hw_notrace(void)
/*
* Interface to various arch routines that may be traced.
*/
#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
static inline void hard_local_irq_disable(void)
{
bfin_cli();
if (!hard_irqs_disabled()) {
__hard_local_irq_disable();
ipipe_trace_begin(0x80000000);
}
}
static inline void local_irq_enable_hw_notrace(void)
static inline void hard_local_irq_enable(void)
{
bfin_sti(bfin_irq_flags);
if (hard_irqs_disabled()) {
ipipe_trace_end(0x80000000);
__hard_local_irq_enable();
}
}
#define local_save_flags_hw(flags) \
do { \
(flags) = bfin_read_IMASK(); \
} while (0)
#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0)
#define irqs_disabled_hw() \
({ \
unsigned long flags; \
local_save_flags_hw(flags); \
irqs_disabled_flags_hw(flags); \
})
static inline void local_irq_save_ptr_hw(unsigned long *flags)
static inline unsigned long hard_local_irq_save(void)
{
*flags = bfin_cli();
#ifdef CONFIG_DEBUG_HWERR
bfin_sti(0x3f);
#endif
unsigned long flags = hard_local_save_flags();
if (!hard_irqs_disabled_flags(flags)) {
__hard_local_irq_disable();
ipipe_trace_begin(0x80000001);
}
return flags;
}
#define local_irq_save_hw_notrace(flags) \
do { \
local_irq_save_ptr_hw(&(flags)); \
} while (0)
static inline void local_irq_restore_hw_notrace(unsigned long flags)
static inline void hard_local_irq_restore(unsigned long flags)
{
if (!irqs_disabled_flags_hw(flags))
local_irq_enable_hw_notrace();
if (!hard_irqs_disabled_flags(flags)) {
ipipe_trace_end(0x80000001);
__hard_local_irq_enable();
}
}
#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
# define local_irq_disable_hw() \
do { \
if (!irqs_disabled_hw()) { \
local_irq_disable_hw_notrace(); \
ipipe_trace_begin(0x80000000); \
} \
} while (0)
# define local_irq_enable_hw() \
do { \
if (irqs_disabled_hw()) { \
ipipe_trace_end(0x80000000); \
local_irq_enable_hw_notrace(); \
} \
} while (0)
# define local_irq_save_hw(flags) \
do { \
local_save_flags_hw(flags); \
if (!irqs_disabled_flags_hw(flags)) { \
local_irq_disable_hw_notrace(); \
ipipe_trace_begin(0x80000001); \
} \
} while (0)
# define local_irq_restore_hw(flags) \
do { \
if (!irqs_disabled_flags_hw(flags)) { \
ipipe_trace_end(0x80000001); \
local_irq_enable_hw_notrace(); \
} \
} while (0)
#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
# define local_irq_disable_hw() local_irq_disable_hw_notrace()
# define local_irq_enable_hw() local_irq_enable_hw_notrace()
# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags)
# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags)
# define hard_local_irq_disable() __hard_local_irq_disable()
# define hard_local_irq_enable() __hard_local_irq_enable()
# define hard_local_irq_save() __hard_local_irq_save()
# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
#else /* CONFIG_IPIPE */
static inline void raw_local_irq_disable(void)
{
bfin_cli();
}
static inline void raw_local_irq_enable(void)
{
bfin_sti(bfin_irq_flags);
}
#define raw_local_save_flags(flags) do { (flags) = bfin_read_IMASK(); } while (0)
#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
/*
* Direct interface to linux/irqflags.h.
*/
#define arch_local_save_flags() hard_local_save_flags()
#define arch_local_irq_save(flags) __hard_local_irq_save()
#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
#define arch_local_irq_enable() __hard_local_irq_enable()
#define arch_local_irq_disable() __hard_local_irq_disable()
#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
#define arch_irqs_disabled() hard_irqs_disabled()
static inline unsigned long __raw_local_irq_save(void)
{
unsigned long flags = bfin_cli();
#ifdef CONFIG_DEBUG_HWERR
bfin_sti(0x3f);
#endif
return flags;
}
#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
/*
* Interface to various arch routines that may be traced.
*/
#define hard_local_irq_save() __hard_local_irq_save()
#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
#define hard_local_irq_enable() __hard_local_irq_enable()
#define hard_local_irq_disable() __hard_local_irq_disable()
#define local_irq_save_hw(flags) raw_local_irq_save(flags)
#define local_irq_restore_hw(flags) raw_local_irq_restore(flags)
#define local_irq_enable_hw() raw_local_irq_enable()
#define local_irq_disable_hw() raw_local_irq_disable()
#define irqs_disabled_hw() irqs_disabled()
#endif /* !CONFIG_IPIPE */
static inline void raw_local_irq_restore(unsigned long flags)
{
if (!raw_irqs_disabled_flags(flags))
raw_local_irq_enable();
}
#endif
arch/blackfin/include/asm/mmu_context.h
View file @ e36f561a
......@@ -97,8 +97,8 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next
}
#ifdef CONFIG_IPIPE
#define lock_mm_switch(flags) local_irq_save_hw_cond(flags)
#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags)
#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
#else
#define lock_mm_switch(flags) do { (void)(flags); } while (0)
#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
......@@ -205,9 +205,9 @@ static inline void destroy_context(struct mm_struct *mm)
}
#define ipipe_mm_switch_protect(flags) \
local_irq_save_hw_cond(flags)
flags = hard_local_irq_save_cond()
#define ipipe_mm_switch_unprotect(flags) \
local_irq_restore_hw_cond(flags)
hard_local_irq_restore_cond(flags)
#endif
arch/blackfin/include/asm/system.h
View file @ e36f561a
......@@ -117,7 +117,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
unsigned long tmp = 0;
unsigned long flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
switch (size) {
case 1:
......@@ -139,7 +139,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
}
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return tmp;
}
......
arch/blackfin/kernel/bfin_gpio.c
View file @ e36f561a
This diff is collapsed.
arch/blackfin/kernel/cplb-mpu/cplbmgr.c
View file @ e36f561a
......@@ -318,7 +318,7 @@ void flush_switched_cplbs(unsigned int cpu)
nr_cplb_flush[cpu]++;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
_disable_icplb();
for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
icplb_tbl[cpu][i].data = 0;
......@@ -332,7 +332,7 @@ void flush_switched_cplbs(unsigned int cpu)
bfin_write32(DCPLB_DATA0 + i * 4, 0);
}
_enable_dcplb();
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
......@@ -348,7 +348,7 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
return;
}
local_irq_save_hw(flags);
flags = hard_local_irq_save();
current_rwx_mask[cpu] = masks;
if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
......@@ -373,5 +373,5 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
addr += PAGE_SIZE;
}
_enable_dcplb();
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
arch/blackfin/kernel/ipipe.c
View file @ e36f561a
......@@ -219,10 +219,10 @@ int __ipipe_syscall_root(struct pt_regs *regs)
ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
local_irq_save_hw(flags);
flags = hard_local_irq_save();
if (!__ipipe_root_domain_p) {
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return 1;
}
......@@ -230,7 +230,7 @@ int __ipipe_syscall_root(struct pt_regs *regs)
if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0)
__ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return -ret;
}
......@@ -239,14 +239,14 @@ unsigned long ipipe_critical_enter(void (*syncfn) (void))
{
unsigned long flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
return flags;
}
void ipipe_critical_exit(unsigned long flags)
{
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
static void __ipipe_no_irqtail(void)
......@@ -279,9 +279,9 @@ int ipipe_trigger_irq(unsigned irq)
return -EINVAL;
#endif
local_irq_save_hw(flags);
flags = hard_local_irq_save();
__ipipe_handle_irq(irq, NULL);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return 1;
}
......@@ -293,7 +293,7 @@ asmlinkage void __ipipe_sync_root(void)
BUG_ON(irqs_disabled());
local_irq_save_hw(flags);
flags = hard_local_irq_save();
if (irq_tail_hook)
irq_tail_hook();
......@@ -303,7 +303,7 @@ asmlinkage void __ipipe_sync_root(void)
if (ipipe_root_cpudom_var(irqpend_himask) != 0)
__ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
void ___ipipe_sync_pipeline(unsigned long syncmask)
......@@ -344,10 +344,10 @@ void __ipipe_stall_root(void)
{
unsigned long *p, flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
__set_bit(IPIPE_STALL_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
EXPORT_SYMBOL(__ipipe_stall_root);
......@@ -356,10 +356,10 @@ unsigned long __ipipe_test_and_stall_root(void)
unsigned long *p, flags;
int x;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return x;
}
......@@ -371,10 +371,10 @@ unsigned long __ipipe_test_root(void)
unsigned long flags;
int x;
local_irq_save_hw_smp(flags);
flags = hard_local_irq_save_smp();
p = &__ipipe_root_status;
x = test_bit(IPIPE_STALL_FLAG, p);
local_irq_restore_hw_smp(flags);
hard_local_irq_restore_smp(flags);
return x;
}
......@@ -384,10 +384,10 @@ void __ipipe_lock_root(void)
{
unsigned long *p, flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
__set_bit(IPIPE_SYNCDEFER_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
EXPORT_SYMBOL(__ipipe_lock_root);
......@@ -395,9 +395,9 @@ void __ipipe_unlock_root(void)
{
unsigned long *p, flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
p = &__ipipe_root_status;
__clear_bit(IPIPE_SYNCDEFER_FLAG, p);
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
EXPORT_SYMBOL(__ipipe_unlock_root);
arch/blackfin/kernel/process.c
View file @ e36f561a
......@@ -65,11 +65,11 @@ static void default_idle(void)
#ifdef CONFIG_IPIPE
ipipe_suspend_domain();
#endif
local_irq_disable_hw();
hard_local_irq_disable();
if (!need_resched())
idle_with_irq_disabled();
local_irq_enable_hw();
hard_local_irq_enable();
}
/*
......
arch/blackfin/kernel/trace.c
View file @ e36f561a
......@@ -15,6 +15,7 @@
#include <linux/kallsyms.h>
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/irq.h>
#include <asm/dma.h>
#include <asm/trace.h>
#include <asm/fixed_code.h>
......
arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
View file @ e36f561a
......@@ -1058,54 +1058,4 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
}
#endif /* _CDEF_BF52X_H */
arch/blackfin/mach-bf518/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
View file @ e36f561a
......@@ -1110,54 +1110,4 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
}
#endif /* _CDEF_BF52X_H */
arch/blackfin/mach-bf527/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-bf533/boards/blackstamp.c
View file @ e36f561a
......@@ -25,6 +25,7 @@
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <mach/fio_flag.h>
/*
* Name the Board for the /proc/cpuinfo
......
arch/blackfin/mach-bf533/boards/ip0x.c
View file @ e36f561a
......@@ -22,6 +22,7 @@
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <mach/fio_flag.h>
/*
* Name the Board for the /proc/cpuinfo
......
arch/blackfin/mach-bf533/boards/stamp.c
View file @ e36f561a
......@@ -24,6 +24,7 @@
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <mach/fio_flag.h>
/*
* Name the Board for the /proc/cpuinfo
......
arch/blackfin/mach-bf533/include/mach/cdefBF532.h
View file @ e36f561a
......@@ -7,11 +7,6 @@
#ifndef _CDEF_BF532_H
#define _CDEF_BF532_H
#include <asm/blackfin.h>
/*include all Core registers and bit definitions*/
#include "defBF532.h"
/*include core specific register pointer definitions*/
#include <asm/cdef_LPBlackfin.h>
......@@ -655,90 +650,4 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
#if ANOMALY_05000311
#define BFIN_WRITE_FIO_FLAG(name) \
static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
{ \
unsigned long flags; \
local_irq_save_hw(flags); \
bfin_write16(FIO_FLAG_##name, val); \
bfin_read_CHIPID(); \
local_irq_restore_hw(flags); \
}
BFIN_WRITE_FIO_FLAG(D)
BFIN_WRITE_FIO_FLAG(C)
BFIN_WRITE_FIO_FLAG(S)
BFIN_WRITE_FIO_FLAG(T)
#define BFIN_READ_FIO_FLAG(name) \
static inline u16 bfin_read_FIO_FLAG_##name(void) \
{ \
unsigned long flags; \
u16 ret; \
local_irq_save_hw(flags); \
ret = bfin_read16(FIO_FLAG_##name); \
bfin_read_CHIPID(); \
local_irq_restore_hw(flags); \
return ret; \
}
BFIN_READ_FIO_FLAG(D)
BFIN_READ_FIO_FLAG(C)
BFIN_READ_FIO_FLAG(S)
BFIN_READ_FIO_FLAG(T)
#else
#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
#endif
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
}
#endif /* _CDEF_BF532_H */
arch/blackfin/mach-bf533/include/mach/fio_flag.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_FIO_FLAG_H
#define _MACH_FIO_FLAG_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
#if ANOMALY_05000311
#define BFIN_WRITE_FIO_FLAG(name) \
static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
{ \
unsigned long flags; \
flags = hard_local_irq_save(); \
bfin_write16(FIO_FLAG_##name, val); \
bfin_read_CHIPID(); \
hard_local_irq_restore(flags); \
}
BFIN_WRITE_FIO_FLAG(D)
BFIN_WRITE_FIO_FLAG(C)
BFIN_WRITE_FIO_FLAG(S)
BFIN_WRITE_FIO_FLAG(T)
#define BFIN_READ_FIO_FLAG(name) \
static inline u16 bfin_read_FIO_FLAG_##name(void) \
{ \
unsigned long flags; \
u16 ret; \
flags = hard_local_irq_save(); \
ret = bfin_read16(FIO_FLAG_##name); \
bfin_read_CHIPID(); \
hard_local_irq_restore(flags); \
return ret; \
}
BFIN_READ_FIO_FLAG(D)
BFIN_READ_FIO_FLAG(C)
BFIN_READ_FIO_FLAG(S)
BFIN_READ_FIO_FLAG(T)
#else
#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
#endif
#endif /* _MACH_FIO_FLAG_H */
arch/blackfin/mach-bf533/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-bf537/include/mach/cdefBF534.h
View file @ e36f561a
......@@ -1750,48 +1750,4 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
local_irq_restore_hw(flags);
}
#endif /* _CDEF_BF534_H */
arch/blackfin/mach-bf537/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR, iwr);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-bf538/include/mach/cdefBF538.h
View file @ e36f561a
......@@ -2027,54 +2027,4 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
local_irq_restore_hw(flags);
}
#endif
arch/blackfin/mach-bf538/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
View file @ e36f561a
......@@ -2648,61 +2648,5 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
iwr2 = bfin_read32(SIC_IWR2);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write32(SIC_IWR2, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
iwr2 = bfin_read32(SIC_IWR2);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write32(SIC_IWR2, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
local_irq_restore_hw(flags);
}
#endif /* _CDEF_BF54X_H */
arch/blackfin/mach-bf548/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
iwr2 = bfin_read32(SIC_IWR2);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write32(SIC_IWR2, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
iwr2 = bfin_read32(SIC_IWR2);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
bfin_write32(SIC_IWR1, 0);
bfin_write32(SIC_IWR2, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-bf561/include/mach/cdefBF561.h
View file @ e36f561a
......@@ -1534,54 +1534,4 @@
/* These need to be last due to the cdef/linux inter-dependencies */
#include <asm/irq.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
bfin_write32(SICA_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
local_irq_restore_hw(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
local_irq_save_hw(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
bfin_write32(SICA_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
local_irq_restore_hw(flags);
}
#endif /* _CDEF_BF561_H */
arch/blackfin/mach-bf561/include/mach/pll.h 0 → 100644
View file @ e36f561a
/*
* Copyright 2005-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#include <asm/blackfin.h>
#include <asm/irqflags.h>
/* Writing to PLL_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_PLL_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
bfin_write32(SICA_IWR1, 0);
bfin_write16(PLL_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
hard_local_irq_restore(flags);
}
/* Writing to VR_CTL initiates a PLL relock sequence. */
static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
if (val == bfin_read_VR_CTL())
return;
flags = hard_local_irq_save();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
/* Only allow PPL Wakeup) */
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
bfin_write32(SICA_IWR1, 0);
bfin_write16(VR_CTL, val);
SSYNC();
asm("IDLE;");
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
hard_local_irq_restore(flags);
}
#endif /* _MACH_PLL_H */
arch/blackfin/mach-common/cpufreq.c
View file @ e36f561a
......@@ -134,7 +134,7 @@ static int bfin_target(struct cpufreq_policy *poli,
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
if (cpu == CPUFREQ_CPU) {
local_irq_save_hw(flags);
flags = hard_local_irq_save();
plldiv = (bfin_read_PLL_DIV() & SSEL) |
dpm_state_table[index].csel;
bfin_write_PLL_DIV(plldiv);
......@@ -155,7 +155,7 @@ static int bfin_target(struct cpufreq_policy *poli,
loops_per_jiffy = cpufreq_scale(lpj_ref,
lpj_ref_freq, freqs.new);
}
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
/* TODO: just test case for cycles clock source, remove later */
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
......
arch/blackfin/mach-common/ints-priority.c
View file @ e36f561a
......@@ -132,8 +132,8 @@ static void bfin_ack_noop(unsigned int irq)
static void bfin_core_mask_irq(unsigned int irq)
{
bfin_irq_flags &= ~(1 << irq);
if (!irqs_disabled_hw())
local_irq_enable_hw();
if (!hard_irqs_disabled())
hard_local_irq_enable();
}
static void bfin_core_unmask_irq(unsigned int irq)
......@@ -148,8 +148,8 @@ static void bfin_core_unmask_irq(unsigned int irq)
* local_irq_enable just does "STI bfin_irq_flags", so it's exactly
* what we need.
*/
if (!irqs_disabled_hw())
local_irq_enable_hw();
if (!hard_irqs_disabled())
hard_local_irq_enable();
return;
}
......@@ -158,12 +158,12 @@ static void bfin_internal_mask_irq(unsigned int irq)
unsigned long flags;
#ifdef CONFIG_BF53x
local_irq_save_hw(flags);
flags = hard_local_irq_save();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 << SIC_SYSIRQ(irq)));
#else
unsigned mask_bank, mask_bit;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
mask_bank = SIC_SYSIRQ(irq) / 32;
mask_bit = SIC_SYSIRQ(irq) % 32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
......@@ -173,7 +173,7 @@ static void bfin_internal_mask_irq(unsigned int irq)
~(1 << mask_bit));
#endif
#endif
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#ifdef CONFIG_SMP
......@@ -186,12 +186,12 @@ static void bfin_internal_unmask_irq(unsigned int irq)
unsigned long flags;
#ifdef CONFIG_BF53x
local_irq_save_hw(flags);
flags = hard_local_irq_save();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
(1 << SIC_SYSIRQ(irq)));
#else
unsigned mask_bank, mask_bit;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
mask_bank = SIC_SYSIRQ(irq) / 32;
mask_bit = SIC_SYSIRQ(irq) % 32;
#ifdef CONFIG_SMP
......@@ -207,7 +207,7 @@ static void bfin_internal_unmask_irq(unsigned int irq)
(1 << mask_bit));
#endif
#endif
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
#ifdef CONFIG_SMP
......@@ -264,7 +264,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
break;
}
local_irq_save_hw(flags);
flags = hard_local_irq_save();
if (state) {
bfin_sic_iwr[bank] |= (1 << bit);
......@@ -275,7 +275,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
vr_wakeup &= ~wakeup;
}
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
return 0;
}
......
arch/blackfin/mach-common/pm.c
View file @ e36f561a
......@@ -25,7 +25,7 @@ void bfin_pm_suspend_standby_enter(void)
{
unsigned long flags;
local_irq_save_hw(flags);
flags = hard_local_irq_save();
bfin_pm_standby_setup();
#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
......@@ -56,7 +56,7 @@ void bfin_pm_suspend_standby_enter(void)
bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
}
int bf53x_suspend_l1_mem(unsigned char *memptr)
......@@ -149,12 +149,12 @@ int bfin_pm_suspend_mem_enter(void)
wakeup |= GPWE;
#endif
local_irq_save_hw(flags);
flags = hard_local_irq_save();
ret = blackfin_dma_suspend();
if (ret) {
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
kfree(memptr);
return ret;
}
......@@ -178,7 +178,7 @@ int bfin_pm_suspend_mem_enter(void)
bfin_gpio_pm_hibernate_restore();
blackfin_dma_resume();
local_irq_restore_hw(flags);
hard_local_irq_restore(flags);
kfree(memptr);
return 0;
......
arch/cris/include/arch-v10/arch/irqflags.h 0 → 100644
View file @ e36f561a
#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
#define __ASM_CRIS_ARCH_IRQFLAGS_H
#include <linux/types.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
asm volatile("di" : : : "memory");
}
static inline void arch_local_irq_enable(void)
{
asm volatile("ei" : : : "memory");
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile("move %0,$ccr" : : "rm" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return !(flags & (1 << 5));
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */
arch/cris/include/arch-v10/arch/system.h
View file @ e36f561a
......@@ -44,20 +44,4 @@ static inline unsigned long _get_base(char * addr)
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((struct __xchg_dummy *)(x))
/* interrupt control.. */
#define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory");
#define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory");
#define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory");
#define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory");
#define irqs_disabled() \
({ \
unsigned long flags; \
local_save_flags(flags); \
!(flags & (1<<5)); \
})
/* For spinlocks etc */
#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory");
#endif
arch/cris/include/arch-v32/arch/irqflags.h 0 → 100644
View file @ e36f561a
#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
#define __ASM_CRIS_ARCH_IRQFLAGS_H
#include <linux/types.h>
#include <arch/ptrace.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("move $ccs,%0" : "=rm" (flags) : : "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
asm volatile("di" : : : "memory");
}
static inline void arch_local_irq_enable(void)
{
asm volatile("ei" : : : "memory");
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile("move %0,$ccs" : : "rm" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return !(flags & (1 << I_CCS_BITNR));
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */
arch/cris/include/arch-v32/arch/system.h
View file @ e36f561a
......@@ -44,26 +44,4 @@ static inline unsigned long rdsp(void)
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((struct __xchg_dummy *)(x))
/* Used for interrupt control. */
#define local_save_flags(x) \
__asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory");
#define local_irq_restore(x) \
__asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory");
#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory");
#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory");
#define irqs_disabled() \
({ \
unsigned long flags; \
\
local_save_flags(flags);\
!(flags & (1 << I_CCS_BITNR)); \
})
/* Used for spinlocks, etc. */
#define local_irq_save(x) \
__asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory");
#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
arch/cris/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
#include <arch/irqflags.h>
arch/cris/include/asm/system.h
View file @ e36f561a
#ifndef __ASM_CRIS_SYSTEM_H
#define __ASM_CRIS_SYSTEM_H
#include <linux/irqflags.h>
#include <arch/system.h>
/* the switch_to macro calls resume, an asm function in entry.S which does the actual
......
arch/frv/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
/* FR-V interrupt handling
*
* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_IRQFLAGS_H
#define _ASM_IRQFLAGS_H
/*
* interrupt flag manipulation
* - use virtual interrupt management since touching the PSR is slow
* - ICC2.Z: T if interrupts virtually disabled
* - ICC2.C: F if interrupts really disabled
* - if Z==1 upon interrupt:
* - C is set to 0
* - interrupts are really disabled
* - entry.S returns immediately
* - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
* - if taken, the trap:
* - sets ICC2.C
* - enables interrupts
*/
static inline void arch_local_irq_disable(void)
{
/* set Z flag, but don't change the C flag */
asm volatile(" andcc gr0,gr0,gr0,icc2 \n"
:
:
: "memory", "icc2"
);
}
static inline void arch_local_irq_enable(void)
{
/* clear Z flag and then test the C flag */
asm volatile(" oricc gr0,#1,gr0,icc2 \n"
" tihi icc2,gr0,#2 \n"
:
:
: "memory", "icc2"
);
}
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("movsg ccr,%0"
: "=r"(flags)
:
: "memory");
/* shift ICC2.Z to bit 0 */
flags >>= 26;
/* make flags 1 if interrupts disabled, 0 otherwise */
return flags & 1UL;
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
/* load the Z flag by turning 1 if disabled into 0 if disabled
* and thus setting the Z flag but not the C flag */
asm volatile(" xoricc %0,#1,gr0,icc2 \n"
/* then trap if Z=0 and C=0 */
" tihi icc2,gr0,#2 \n"
:
: "r"(flags)
: "memory", "icc2"
);
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return flags;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
/*
* real interrupt flag manipulation
*/
#define __arch_local_irq_disable() \
do { \
unsigned long psr; \
asm volatile(" movsg psr,%0 \n" \
" andi %0,%2,%0 \n" \
" ori %0,%1,%0 \n" \
" movgs %0,psr \n" \
: "=r"(psr) \
: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
: "memory"); \
} while (0)
#define __arch_local_irq_enable() \
do { \
unsigned long psr; \
asm volatile(" movsg psr,%0 \n" \
" andi %0,%1,%0 \n" \
" movgs %0,psr \n" \
: "=r"(psr) \
: "i" (~PSR_PIL) \
: "memory"); \
} while (0)
#define __arch_local_save_flags(flags) \
do { \
typecheck(unsigned long, flags); \
asm("movsg psr,%0" \
: "=r"(flags) \
: \
: "memory"); \
} while (0)
#define __arch_local_irq_save(flags) \
do { \
unsigned long npsr; \
typecheck(unsigned long, flags); \
asm volatile(" movsg psr,%0 \n" \
" andi %0,%3,%1 \n" \
" ori %1,%2,%1 \n" \
" movgs %1,psr \n" \
: "=r"(flags), "=r"(npsr) \
: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
: "memory"); \
} while (0)
#define __arch_local_irq_restore(flags) \
do { \
typecheck(unsigned long, flags); \
asm volatile(" movgs %0,psr \n" \
: \
: "r" (flags) \
: "memory"); \
} while (0)
#define __arch_irqs_disabled() \
((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
#endif /* _ASM_IRQFLAGS_H */
arch/frv/include/asm/system.h
View file @ e36f561a
......@@ -36,142 +36,6 @@ do { \
mb(); \
} while(0)
/*
* interrupt flag manipulation
* - use virtual interrupt management since touching the PSR is slow
* - ICC2.Z: T if interrupts virtually disabled
* - ICC2.C: F if interrupts really disabled
* - if Z==1 upon interrupt:
* - C is set to 0
* - interrupts are really disabled
* - entry.S returns immediately
* - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
* - if taken, the trap:
* - sets ICC2.C
* - enables interrupts
*/
#define local_irq_disable() \
do { \
/* set Z flag, but don't change the C flag */ \
asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \
: \
: \
: "memory", "icc2" \
); \
} while(0)
#define local_irq_enable() \
do { \
/* clear Z flag and then test the C flag */ \
asm volatile(" oricc gr0,#1,gr0,icc2 \n" \
" tihi icc2,gr0,#2 \n" \
: \
: \
: "memory", "icc2" \
); \
} while(0)
#define local_save_flags(flags) \
do { \
typecheck(unsigned long, flags); \
asm volatile("movsg ccr,%0" \
: "=r"(flags) \
: \
: "memory"); \
\
/* shift ICC2.Z to bit 0 */ \
flags >>= 26; \
\
/* make flags 1 if interrupts disabled, 0 otherwise */ \
flags &= 1UL; \
} while(0)
#define irqs_disabled() \
({unsigned long flags; local_save_flags(flags); !!flags; })
#define local_irq_save(flags) \
do { \
typecheck(unsigned long, flags); \
local_save_flags(flags); \
local_irq_disable(); \
} while(0)
#define local_irq_restore(flags) \
do { \
typecheck(unsigned long, flags); \
\
/* load the Z flag by turning 1 if disabled into 0 if disabled \
* and thus setting the Z flag but not the C flag */ \
asm volatile(" xoricc %0,#1,gr0,icc2 \n" \
/* then test Z=0 and C=0 */ \
" tihi icc2,gr0,#2 \n" \
: \
: "r"(flags) \
: "memory", "icc2" \
); \
\
} while(0)
/*
* real interrupt flag manipulation
*/
#define __local_irq_disable() \
do { \
unsigned long psr; \
asm volatile(" movsg psr,%0 \n" \
" andi %0,%2,%0 \n" \
" ori %0,%1,%0 \n" \
" movgs %0,psr \n" \
: "=r"(psr) \
: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
: "memory"); \
} while(0)
#define __local_irq_enable() \
do { \
unsigned long psr; \
asm volatile(" movsg psr,%0 \n" \
" andi %0,%1,%0 \n" \
" movgs %0,psr \n" \
: "=r"(psr) \
: "i" (~PSR_PIL) \
: "memory"); \
} while(0)
#define __local_save_flags(flags) \
do { \
typecheck(unsigned long, flags); \
asm("movsg psr,%0" \
: "=r"(flags) \
: \
: "memory"); \
} while(0)
#define __local_irq_save(flags) \
do { \
unsigned long npsr; \
typecheck(unsigned long, flags); \
asm volatile(" movsg psr,%0 \n" \
" andi %0,%3,%1 \n" \
" ori %1,%2,%1 \n" \
" movgs %1,psr \n" \
: "=r"(flags), "=r"(npsr) \
: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
: "memory"); \
} while(0)
#define __local_irq_restore(flags) \
do { \
typecheck(unsigned long, flags); \
asm volatile(" movgs %0,psr \n" \
: \
: "r" (flags) \
: "memory"); \
} while(0)
#define __irqs_disabled() \
((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
/*
* Force strict CPU ordering.
*/
......
arch/h8300/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
#ifndef _H8300_IRQFLAGS_H
#define _H8300_IRQFLAGS_H
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile ("stc ccr,%w0" : "=r" (flags));
return flags;
}
static inline void arch_local_irq_disable(void)
{
asm volatile ("orc #0x80,ccr" : : : "memory");
}
static inline void arch_local_irq_enable(void)
{
asm volatile ("andc #0x7f,ccr" : : : "memory");
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile ("ldc %w0,ccr" : : "r" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & 0x80) == 0x80;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* _H8300_IRQFLAGS_H */
arch/h8300/include/asm/system.h
View file @ e36f561a
......@@ -2,6 +2,7 @@
#define _H8300_SYSTEM_H
#include <linux/linkage.h>
#include <linux/irqflags.h>
struct pt_regs;
......@@ -51,31 +52,8 @@ asmlinkage void resume(void);
(last) = _last; \
}
#define __sti() asm volatile ("andc #0x7f,ccr")
#define __cli() asm volatile ("orc #0x80,ccr")
#define __save_flags(x) \
asm volatile ("stc ccr,%w0":"=r" (x))
#define __restore_flags(x) \
asm volatile ("ldc %w0,ccr": :"r" (x))
#define irqs_disabled() \
({ \
unsigned char flags; \
__save_flags(flags); \
((flags & 0x80) == 0x80); \
})
#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
/* For spinlocks etc */
#define local_irq_disable() __cli()
#define local_irq_enable() __sti()
#define local_irq_save(x) ({ __save_flags(x); local_irq_disable(); })
#define local_irq_restore(x) __restore_flags(x)
#define local_save_flags(x) __save_flags(x)
/*
* Force strict CPU ordering.
* Not really required on H8...
......
arch/ia64/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
/*
* IRQ flags defines.
*
* Copyright (C) 1998-2003 Hewlett-Packard Co
* David Mosberger-Tang <davidm@hpl.hp.com>
* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
*/
#ifndef _ASM_IA64_IRQFLAGS_H
#define _ASM_IA64_IRQFLAGS_H
#ifdef CONFIG_IA64_DEBUG_IRQ
extern unsigned long last_cli_ip;
static inline void arch_maybe_save_ip(unsigned long flags)
{
if (flags & IA64_PSR_I)
last_cli_ip = ia64_getreg(_IA64_REG_IP);
}
#else
#define arch_maybe_save_ip(flags) do {} while (0)
#endif
/*
* - clearing psr.i is implicitly serialized (visible by next insn)
* - setting psr.i requires data serialization
* - we need a stop-bit before reading PSR because we sometimes
* write a floating-point register right before reading the PSR
* and that writes to PSR.mfl
*/
static inline unsigned long arch_local_save_flags(void)
{
ia64_stop();
#ifdef CONFIG_PARAVIRT
return ia64_get_psr_i();
#else
return ia64_getreg(_IA64_REG_PSR);
#endif
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
ia64_stop();
ia64_rsm(IA64_PSR_I);
arch_maybe_save_ip(flags);
return flags;
}
static inline void arch_local_irq_disable(void)
{
#ifdef CONFIG_IA64_DEBUG_IRQ
arch_local_irq_save();
#else
ia64_stop();
ia64_rsm(IA64_PSR_I);
#endif
}
static inline void arch_local_irq_enable(void)
{
ia64_stop();
ia64_ssm(IA64_PSR_I);
ia64_srlz_d();
}
static inline void arch_local_irq_restore(unsigned long flags)
{
#ifdef CONFIG_IA64_DEBUG_IRQ
unsigned long old_psr = arch_local_save_flags();
#endif
ia64_intrin_local_irq_restore(flags & IA64_PSR_I);
arch_maybe_save_ip(old_psr & ~flags);
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & IA64_PSR_I) == 0;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
static inline void arch_safe_halt(void)
{
ia64_pal_halt_light(); /* PAL_HALT_LIGHT */
}
#endif /* _ASM_IA64_IRQFLAGS_H */
arch/ia64/include/asm/system.h
View file @ e36f561a
......@@ -107,87 +107,11 @@ extern struct ia64_boot_param {
*/
#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
#define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
/*
* The group barrier in front of the rsm & ssm are necessary to ensure
* that none of the previous instructions in the same group are
* affected by the rsm/ssm.
*/
/* For spinlocks etc */
/*
* - clearing psr.i is implicitly serialized (visible by next insn)
* - setting psr.i requires data serialization
* - we need a stop-bit before reading PSR because we sometimes
* write a floating-point register right before reading the PSR
* and that writes to PSR.mfl
*/
#ifdef CONFIG_PARAVIRT
#define __local_save_flags() ia64_get_psr_i()
#else
#define __local_save_flags() ia64_getreg(_IA64_REG_PSR)
#endif
#define __local_irq_save(x) \
do { \
ia64_stop(); \
(x) = __local_save_flags(); \
ia64_stop(); \
ia64_rsm(IA64_PSR_I); \
} while (0)
#define __local_irq_disable() \
do { \
ia64_stop(); \
ia64_rsm(IA64_PSR_I); \
} while (0)
#define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
#ifdef CONFIG_IA64_DEBUG_IRQ
extern unsigned long last_cli_ip;
# define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
# define local_irq_save(x) \
do { \
unsigned long __psr; \
\
__local_irq_save(__psr); \
if (__psr & IA64_PSR_I) \
__save_ip(); \
(x) = __psr; \
} while (0)
# define local_irq_disable() do { unsigned long __x; local_irq_save(__x); } while (0)
# define local_irq_restore(x) \
do { \
unsigned long __old_psr, __psr = (x); \
\
local_save_flags(__old_psr); \
__local_irq_restore(__psr); \
if ((__old_psr & IA64_PSR_I) && !(__psr & IA64_PSR_I)) \
__save_ip(); \
} while (0)
#else /* !CONFIG_IA64_DEBUG_IRQ */
# define local_irq_save(x) __local_irq_save(x)
# define local_irq_disable() __local_irq_disable()
# define local_irq_restore(x) __local_irq_restore(x)
#endif /* !CONFIG_IA64_DEBUG_IRQ */
#define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
#define local_save_flags(flags) ({ ia64_stop(); (flags) = __local_save_flags(); })
#define irqs_disabled() \
({ \
unsigned long __ia64_id_flags; \
local_save_flags(__ia64_id_flags); \
(__ia64_id_flags & IA64_PSR_I) == 0; \
})
#ifdef __KERNEL__
......
arch/m32r/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
*/
#ifndef _ASM_M32R_IRQFLAGS_H
#define _ASM_M32R_IRQFLAGS_H
#include <linux/types.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("mvfc %0,psw" : "=r"(flags));
return flags;
}
static inline void arch_local_irq_disable(void)
{
#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
asm volatile (
"clrpsw #0x40 -> nop"
: : : "memory");
#else
unsigned long tmpreg0, tmpreg1;
asm volatile (
"ld24 %0, #0 ; Use 32-bit insn. \n\t"
"mvfc %1, psw ; No interrupt can be accepted here. \n\t"
"mvtc %0, psw \n\t"
"and3 %0, %1, #0xffbf \n\t"
"mvtc %0, psw \n\t"
: "=&r" (tmpreg0), "=&r" (tmpreg1)
:
: "cbit", "memory");
#endif
}
static inline void arch_local_irq_enable(void)
{
#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
asm volatile (
"setpsw #0x40 -> nop"
: : : "memory");
#else
unsigned long tmpreg;
asm volatile (
"mvfc %0, psw; \n\t"
"or3 %0, %0, #0x0040; \n\t"
"mvtc %0, psw; \n\t"
: "=&r" (tmpreg)
:
: "cbit", "memory");
#endif
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
asm volatile (
"mvfc %0, psw; \n\t"
"clrpsw #0x40 -> nop; \n\t"
: "=r" (flags)
:
: "memory");
#else
unsigned long tmpreg;
asm volatile (
"ld24 %1, #0 \n\t"
"mvfc %0, psw \n\t"
"mvtc %1, psw \n\t"
"and3 %1, %0, #0xffbf \n\t"
"mvtc %1, psw \n\t"
: "=r" (flags), "=&r" (tmpreg)
:
: "cbit", "memory");
#endif
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile("mvtc %0,psw"
:
: "r" (flags)
: "cbit", "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return !(flags & 0x40);
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* _ASM_M32R_IRQFLAGS_H */
arch/m32r/include/asm/system.h
View file @ e36f561a
......@@ -11,6 +11,7 @@
*/
#include <linux/compiler.h>
#include <linux/irqflags.h>
#include <asm/assembler.h>
#ifdef __KERNEL__
......@@ -54,71 +55,6 @@
); \
} while(0)
/* Interrupt Control */
#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
#define local_irq_enable() \
__asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
#define local_irq_disable() \
__asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
static inline void local_irq_enable(void)
{
unsigned long tmpreg;
__asm__ __volatile__(
"mvfc %0, psw; \n\t"
"or3 %0, %0, #0x0040; \n\t"
"mvtc %0, psw; \n\t"
: "=&r" (tmpreg) : : "cbit", "memory");
}
static inline void local_irq_disable(void)
{
unsigned long tmpreg0, tmpreg1;
__asm__ __volatile__(
"ld24 %0, #0 ; Use 32-bit insn. \n\t"
"mvfc %1, psw ; No interrupt can be accepted here. \n\t"
"mvtc %0, psw \n\t"
"and3 %0, %1, #0xffbf \n\t"
"mvtc %0, psw \n\t"
: "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
}
#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
#define local_save_flags(x) \
__asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
#define local_irq_restore(x) \
__asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
: "r" (x) : "cbit", "memory")
#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
#define local_irq_save(x) \
__asm__ __volatile__( \
"mvfc %0, psw; \n\t" \
"clrpsw #0x40 -> nop; \n\t" \
: "=r" (x) : /* no input */ : "memory")
#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
#define local_irq_save(x) \
({ \
unsigned long tmpreg; \
__asm__ __volatile__( \
"ld24 %1, #0 \n\t" \
"mvfc %0, psw \n\t" \
"mvtc %1, psw \n\t" \
"and3 %1, %0, #0xffbf \n\t" \
"mvtc %1, psw \n\t" \
: "=r" (x), "=&r" (tmpreg) \
: : "cbit", "memory"); \
})
#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
#define irqs_disabled() \
({ \
unsigned long flags; \
local_save_flags(flags); \
!(flags & 0x40); \
})
#define nop() __asm__ __volatile__ ("nop" : : )
#define xchg(ptr, x) \
......
arch/m68k/include/asm/entry_no.h
View file @ e36f561a
......@@ -28,7 +28,7 @@
* M68K COLDFIRE
*/
#define ALLOWINT 0xf8ff
#define ALLOWINT (~0x700)
#ifdef __ASSEMBLY__
......
arch/m68k/include/asm/irqflags.h 0 → 100644
View file @ e36f561a
#ifndef _M68K_IRQFLAGS_H
#define _M68K_IRQFLAGS_H
#include <linux/types.h>
#include <linux/hardirq.h>
#include <linux/preempt.h>
#include <asm/thread_info.h>
#include <asm/entry.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile ("movew %%sr,%0" : "=d" (flags) : : "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
#ifdef CONFIG_COLDFIRE
asm volatile (
"move %/sr,%%d0 \n\t"
"ori.l #0x0700,%%d0 \n\t"
"move %%d0,%/sr \n"
: /* no outputs */
:
: "cc", "%d0", "memory");
#else
asm volatile ("oriw #0x0700,%%sr" : : : "memory");
#endif
}
static inline void arch_local_irq_enable(void)
{
#if defined(CONFIG_COLDFIRE)
asm volatile (
"move %/sr,%%d0 \n\t"
"andi.l #0xf8ff,%%d0 \n\t"
"move %%d0,%/sr \n"
: /* no outputs */
:
: "cc", "%d0", "memory");
#else
# if defined(CONFIG_MMU)
if (MACH_IS_Q40 || !hardirq_count())
# endif
asm volatile (
"andiw %0,%%sr"
:
: "i" (ALLOWINT)
: "memory");
#endif
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile ("movew %0,%%sr" : : "d" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & ~ALLOWINT) != 0;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* _M68K_IRQFLAGS_H */
arch/m68k/include/asm/system_mm.h
View file @ e36f561a
......@@ -3,6 +3,7 @@
#include <linux/linkage.h>
#include <linux/kernel.h>
#include <linux/irqflags.h>
#include <asm/segment.h>
#include <asm/entry.h>
......@@ -62,30 +63,6 @@ asmlinkage void resume(void);
#define smp_wmb() barrier()
#define smp_read_barrier_depends() ((void)0)
/* interrupt control.. */
#if 0
#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
#else
#include <linux/hardirq.h>
#define local_irq_enable() ({ \
if (MACH_IS_Q40 || !hardirq_count()) \
asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \
})
#endif
#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
static inline int irqs_disabled(void)
{
unsigned long flags;
local_save_flags(flags);
return flags & ~ALLOWINT;
}
/* For spinlocks etc */
#define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); })
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
struct __xchg_dummy { unsigned long a[100]; };
......
arch/m68k/include/asm/system_no.h
View file @ e36f561a
......@@ -2,6 +2,7 @@
#define _M68KNOMMU_SYSTEM_H
#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/segment.h>
#include <asm/entry.h>
......@@ -46,54 +47,6 @@ asmlinkage void resume(void);
(last) = _last; \
}
#ifdef CONFIG_COLDFIRE
#define local_irq_enable() __asm__ __volatile__ ( \
"move %/sr,%%d0\n\t" \
"andi.l #0xf8ff,%%d0\n\t" \
"move %%d0,%/sr\n" \
: /* no outputs */ \
: \
: "cc", "%d0", "memory")
#define local_irq_disable() __asm__ __volatile__ ( \
"move %/sr,%%d0\n\t" \
"ori.l #0x0700,%%d0\n\t" \
"move %%d0,%/sr\n" \
: /* no outputs */ \
: \
: "cc", "%d0", "memory")
/* For spinlocks etc */
#define local_irq_save(x) __asm__ __volatile__ ( \
"movew %%sr,%0\n\t" \
"movew #0x0700,%%d0\n\t" \
"or.l %0,%%d0\n\t" \
"movew %%d0,%/sr" \
: "=d" (x) \
: \
: "cc", "%d0", "memory")
#else
/* portable version */ /* FIXME - see entry.h*/
#define ALLOWINT 0xf8ff
#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
#endif
#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
/* For spinlocks etc */
#ifndef local_irq_save
#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
#endif
#define irqs_disabled() \
({ \
unsigned long flags; \
local_save_flags(flags); \
((flags & 0x0700) == 0x0700); \
})
#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
/*
......@@ -206,12 +159,4 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
#define arch_align_stack(x) (x)
static inline int irqs_disabled_flags(unsigned long flags)
{
if (flags & 0x0700)
return 0;
else
return 1;
}
#endif /* _M68KNOMMU_SYSTEM_H */
arch/m68knommu/kernel/asm-offsets.c
View file @ e36f561a
......@@ -74,8 +74,6 @@ int main(void)
DEFINE(PT_PTRACED, PT_PTRACED);
DEFINE(THREAD_SIZE, THREAD_SIZE);
/* Offsets in thread_info structure */
DEFINE(TI_TASK, offsetof(struct thread_info, task));
DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain));
......
arch/m68knommu/platform/coldfire/head.S
View file @ e36f561a
......@@ -15,6 +15,7 @@
#include <asm/coldfire.h>
#include <asm/mcfcache.h>
#include <asm/mcfsim.h>
#include <asm/thread_info.h>
/*****************************************************************************/
......
arch/microblaze/include/asm/irqflags.h
View file @ e36f561a
......@@ -9,103 +9,114 @@
#ifndef _ASM_MICROBLAZE_IRQFLAGS_H
#define _ASM_MICROBLAZE_IRQFLAGS_H
#include <linux/irqflags.h>
#include <linux/types.h>
#include <asm/registers.h>
# if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
# define raw_local_irq_save(flags) \
do { \
asm volatile (" msrclr %0, %1; \
nop;" \
: "=r"(flags) \
: "i"(MSR_IE) \
: "memory"); \
} while (0)
# define raw_local_irq_disable() \
do { \
asm volatile (" msrclr r0, %0; \
nop;" \
: \
: "i"(MSR_IE) \
: "memory"); \
} while (0)
# define raw_local_irq_enable() \
do { \
asm volatile (" msrset r0, %0; \
nop;" \
: \
: "i"(MSR_IE) \
: "memory"); \
} while (0)
# else /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 0 */
# define raw_local_irq_save(flags) \
do { \
register unsigned tmp; \
asm volatile (" mfs %0, rmsr; \
nop; \
andi %1, %0, %2; \
mts rmsr, %1; \
nop;" \
: "=r"(flags), "=r" (tmp) \
: "i"(~MSR_IE) \
: "memory"); \
} while (0)
# define raw_local_irq_disable() \
do { \
register unsigned tmp; \
asm volatile (" mfs %0, rmsr; \
nop; \
andi %0, %0, %1; \
mts rmsr, %0; \
nop;" \
: "=r"(tmp) \
: "i"(~MSR_IE) \
: "memory"); \
} while (0)
# define raw_local_irq_enable() \
do { \
register unsigned tmp; \
asm volatile (" mfs %0, rmsr; \
nop; \
ori %0, %0, %1; \
mts rmsr, %0; \
nop;" \
: "=r"(tmp) \
: "i"(MSR_IE) \
: "memory"); \
} while (0)
# endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
#define raw_local_irq_restore(flags) \
do { \
asm volatile (" mts rmsr, %0; \
nop;" \
: \
: "r"(flags) \
: "memory"); \
} while (0)
static inline unsigned long get_msr(void)
#ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
asm volatile(" msrclr %0, %1 \n"
" nop \n"
: "=r"(flags)
: "i"(MSR_IE)
: "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
/* this uses r0 without declaring it - is that correct? */
asm volatile(" msrclr r0, %0 \n"
" nop \n"
:
: "i"(MSR_IE)
: "memory");
}
static inline void arch_local_irq_enable(void)
{
/* this uses r0 without declaring it - is that correct? */
asm volatile(" msrset r0, %0 \n"
" nop \n"
:
: "i"(MSR_IE)
: "memory");
}
#else /* !CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags, tmp;
asm volatile (" mfs %0, rmsr \n"
" nop \n"
" andi %1, %0, %2 \n"
" mts rmsr, %1 \n"
" nop \n"
: "=r"(flags), "=r"(tmp)
: "i"(~MSR_IE)
: "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
unsigned long tmp;
asm volatile(" mfs %0, rmsr \n"
" nop \n"
" andi %0, %0, %1 \n"
" mts rmsr, %0 \n"
" nop \n"
: "=r"(tmp)
: "i"(~MSR_IE)
: "memory");
}
static inline void arch_local_irq_enable(void)
{
unsigned long tmp;
asm volatile(" mfs %0, rmsr \n"
" nop \n"
" ori %0, %0, %1 \n"
" mts rmsr, %0 \n"
" nop \n"
: "=r"(tmp)
: "i"(MSR_IE)
: "memory");
}
#endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile (" mfs %0, rmsr; \
nop;" \
: "=r"(flags) \
: \
: "memory"); \
asm volatile(" mfs %0, rmsr \n"
" nop \n"
: "=r"(flags)
:
: "memory");
return flags;
}
#define raw_local_save_flags(flags) ((flags) = get_msr())
#define raw_irqs_disabled() ((get_msr() & MSR_IE) == 0)
#define raw_irqs_disabled_flags(flags) ((flags & MSR_IE) == 0)
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile(" mts rmsr, %0 \n"
" nop \n"
:
: "r"(flags)
: "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & MSR_IE) == 0;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* _ASM_MICROBLAZE_IRQFLAGS_H */
arch/mips/alchemy/devboards/bcsr.c
View file @ e36f561a
......@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/mach-db1x00/bcsr.h>
......
arch/mips/ar7/irq.c
View file @ e36f561a
......@@ -19,6 +19,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
......
arch/mips/bcm63xx/irq.c
View file @ e36f561a
......@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
......
arch/mips/cavium-octeon/serial.c
View file @ e36f561a
......@@ -13,6 +13,7 @@
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/tty.h>
#include <linux/irq.h>
#include <asm/time.h>
......
arch/mips/dec/setup.c
View file @ e36f561a
......@@ -18,6 +18,7 @@
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/pm.h>
#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
......
arch/mips/include/asm/irqflags.h
View file @ e36f561a
......@@ -17,7 +17,7 @@
#include <asm/hazards.h>
__asm__(
" .macro raw_local_irq_enable \n"
" .macro arch_local_irq_enable \n"
" .set push \n"
" .set reorder \n"
" .set noat \n"
......@@ -40,7 +40,7 @@ __asm__(
extern void smtc_ipi_replay(void);
static inline void raw_local_irq_enable(void)
static inline void arch_local_irq_enable(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
/*
......@@ -50,7 +50,7 @@ static inline void raw_local_irq_enable(void)
smtc_ipi_replay();
#endif
__asm__ __volatile__(
"raw_local_irq_enable"
"arch_local_irq_enable"
: /* no outputs */
: /* no inputs */
: "memory");
......@@ -76,7 +76,7 @@ static inline void raw_local_irq_enable(void)
* Workaround: mask EXL bit of the result or place a nop before mfc0.
*/
__asm__(
" .macro raw_local_irq_disable\n"
" .macro arch_local_irq_disable\n"
" .set push \n"
" .set noat \n"
#ifdef CONFIG_MIPS_MT_SMTC
......@@ -97,17 +97,17 @@ __asm__(
" .set pop \n"
" .endm \n");
static inline void raw_local_irq_disable(void)
static inline void arch_local_irq_disable(void)
{
__asm__ __volatile__(
"raw_local_irq_disable"
"arch_local_irq_disable"
: /* no outputs */
: /* no inputs */
: "memory");
}
__asm__(
" .macro raw_local_save_flags flags \n"
" .macro arch_local_save_flags flags \n"
" .set push \n"
" .set reorder \n"
#ifdef CONFIG_MIPS_MT_SMTC
......@@ -118,13 +118,15 @@ __asm__(
" .set pop \n"
" .endm \n");
#define raw_local_save_flags(x) \
__asm__ __volatile__( \
"raw_local_save_flags %0" \
: "=r" (x))
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("arch_local_save_flags %0" : "=r" (flags));
return flags;
}
__asm__(
" .macro raw_local_irq_save result \n"
" .macro arch_local_irq_save result \n"
" .set push \n"
" .set reorder \n"
" .set noat \n"
......@@ -148,15 +150,18 @@ __asm__(
" .set pop \n"
" .endm \n");
#define raw_local_irq_save(x) \
__asm__ __volatile__( \
"raw_local_irq_save\t%0" \
: "=r" (x) \
: /* no inputs */ \
: "memory")
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
asm volatile("arch_local_irq_save\t%0"
: "=r" (flags)
: /* no inputs */
: "memory");
return flags;
}
__asm__(
" .macro raw_local_irq_restore flags \n"
" .macro arch_local_irq_restore flags \n"
" .set push \n"
" .set noreorder \n"
" .set noat \n"
......@@ -196,7 +201,7 @@ __asm__(
" .endm \n");
static inline void raw_local_irq_restore(unsigned long flags)
static inline void arch_local_irq_restore(unsigned long flags)
{
unsigned long __tmp1;
......@@ -211,24 +216,24 @@ static inline void raw_local_irq_restore(unsigned long flags)
#endif
__asm__ __volatile__(
"raw_local_irq_restore\t%0"
"arch_local_irq_restore\t%0"
: "=r" (__tmp1)
: "0" (flags)
: "memory");
}
static inline void __raw_local_irq_restore(unsigned long flags)
static inline void __arch_local_irq_restore(unsigned long flags)
{
unsigned long __tmp1;
__asm__ __volatile__(
"raw_local_irq_restore\t%0"
"arch_local_irq_restore\t%0"
: "=r" (__tmp1)
: "0" (flags)
: "memory");
}
static inline int raw_irqs_disabled_flags(unsigned long flags)
static inline int arch_irqs_disabled_flags(unsigned long flags)
{
#ifdef CONFIG_MIPS_MT_SMTC
/*
......
arch/mips/include/asm/mach-loongson/loongson.h
View file @ e36f561a
......@@ -13,6 +13,7 @@
#include <linux/io.h>
#include <linux/init.h>
#include <linux/irq.h>
/* loongson internal northbridge initialization */
extern void bonito_irq_init(void);
......
arch/mips/jazz/irq.c
View file @ e36f561a
......@@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/i8253.h>
......
arch/mips/kernel/cevt-bcm1480.c
View file @ e36f561a
......@@ -19,6 +19,7 @@
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/irq.h>
#include <asm/addrspace.h>
#include <asm/io.h>
......
arch/mips/kernel/cevt-ds1287.c
View file @ e36f561a
......@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/irq.h>
#include <asm/time.h>
......
arch/mips/kernel/cevt-gt641xx.c
View file @ e36f561a
......@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/gt64120.h>
#include <asm/time.h>
......
arch/mips/kernel/cevt-r4k.c
View file @ e36f561a
......@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/irq.h>
#include <asm/smtc_ipi.h>
#include <asm/time.h>
......
arch/mips/kernel/cevt-sb1250.c
View file @ e36f561a
......@@ -17,6 +17,7 @@
*/
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/percpu.h>
#include <linux/smp.h>
......
arch/mips/kernel/cevt-smtc.c
View file @ e36f561a
......@@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/irq.h>
#include <asm/smtc_ipi.h>
#include <asm/time.h>
......
arch/mips/kernel/cevt-txx9.c
View file @ e36f561a
......@@ -13,6 +13,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/time.h>
#include <asm/txx9tmr.h>
......
arch/mips/kernel/i8253.c
View file @ e36f561a
......@@ -9,6 +9,7 @@
#include <linux/module.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/delay.h>
#include <asm/i8253.h>
......
arch/mips/kernel/i8259.c
View file @ e36f561a
......@@ -15,6 +15,7 @@
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/sysdev.h>
#include <linux/irq.h>
#include <asm/i8259.h>
#include <asm/io.h>
......
arch/mips/kernel/irq-gic.c
View file @ e36f561a
......@@ -3,11 +3,11 @@
#include <linux/bitmap.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/gic.h>
#include <asm/gcmpregs.h>
#include <asm/irq.h>
#include <linux/hardirq.h>
#include <asm-generic/bitops/find.h>
......
arch/mips/kernel/irq-rm7000.c
View file @ e36f561a
......@@ -11,6 +11,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <asm/irq_cpu.h>
......
arch/mips/kernel/irq-rm9000.c
View file @ e36f561a
......@@ -11,6 +11,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
......
arch/mips/kernel/irq_cpu.c
View file @ e36f561a
......@@ -30,6 +30,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
......
arch/mips/kernel/irq_txx9.c
View file @ e36f561a
......@@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <asm/txx9irq.h>
struct txx9_irc_reg {
......
arch/mips/kernel/smtc.c
View file @ e36f561a
......@@ -1038,7 +1038,7 @@ void deferred_smtc_ipi(void)
* but it's more efficient, given that we're already
* running down the IPI queue.
*/
__raw_local_irq_restore(flags);
__arch_local_irq_restore(flags);
}
}
......@@ -1190,7 +1190,7 @@ void smtc_ipi_replay(void)
/*
** But use a raw restore here to avoid recursion.
*/
__raw_local_irq_restore(flags);
__arch_local_irq_restore(flags);
if (pipi) {
self_ipi(pipi);
......
arch/mips/kernel/traps.c
View file @ e36f561a
......@@ -28,6 +28,7 @@
#include <linux/kprobes.h>
#include <linux/notifier.h>
#include <linux/kdb.h>
#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/branch.h>
......@@ -51,7 +52,6 @@
#include <asm/mmu_context.h>
#include <asm/types.h>
#include <asm/stacktrace.h>
#include <asm/irq.h>
#include <asm/uasm.h>
extern void check_wait(void);
......
arch/mips/mti-malta/malta-platform.c
View file @ e36f561a
......@@ -25,6 +25,7 @@
#include <linux/serial_8250.h>
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
......
arch/mips/pci/ops-tx3927.c
View file @ e36f561a
......@@ -38,6 +38,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/addrspace.h>
#include <asm/txx9irq.h>
......
arch/mips/pci/ops-tx4927.c
View file @ e36f561a
......@@ -17,6 +17,7 @@
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/txx9/pci.h>
#include <asm/txx9/tx4927pcic.h>
......
arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
View file @ e36f561a
......@@ -14,6 +14,7 @@
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <asm/system.h>
......
arch/mips/powertv/asic/irq_asic.c
View file @ e36f561a
......@@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
......
arch/mips/rb532/serial.c
View file @ e36f561a
......@@ -29,6 +29,7 @@
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/irq.h>
#include <asm/serial.h>
#include <asm/mach-rc32434/rb.h>
......
arch/mips/sni/a20r.c
View file @ e36f561a
......@@ -10,6 +10,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
......
arch/mips/sni/pcimt.c
View file @ e36f561a
......@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>
......
arch/mips/sni/pcit.c
View file @ e36f561a
......@@ -10,6 +10,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>
......
arch/mips/sni/rm200.c
View file @ e36f561a
......@@ -13,6 +13,7 @@
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
......
arch/mips/sni/time.c
View file @ e36f561a
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/time.h>
#include <linux/clockchips.h>
......
arch/mips/txx9/generic/irq_tx4927.c
View file @ e36f561a
......@@ -25,6 +25,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/txx9/tx4927.h>
......
arch/mips/txx9/generic/irq_tx4938.c
View file @ e36f561a
......@@ -13,6 +13,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/txx9/tx4938.h>
......
arch/mips/txx9/generic/irq_tx4939.c
View file @ e36f561a
......@@ -19,6 +19,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <asm/irq_cpu.h>
#include <asm/txx9irq.h>
......
arch/mips/txx9/generic/setup.c
View file @ e36f561a
......@@ -24,6 +24,7 @@
#include <linux/leds.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/reboot.h>
......
arch/mips/txx9/jmr3927/irq.c
View file @ e36f561a
......@@ -32,6 +32,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
......
arch/mips/txx9/rbtx4927/irq.c
View file @ e36f561a
......@@ -111,6 +111,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/txx9/generic.h>
......
arch/mips/txx9/rbtx4938/irq.c
View file @ e36f561a
......@@ -64,6 +64,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/rbtx4938.h>
......
arch/mips/txx9/rbtx4939/irq.c
View file @ e36f561a
......@@ -11,6 +11,7 @@
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/txx9/rbtx4939.h>
......
arch/mips/vr41xx/common/irq.c
View file @ e36f561a
......@@ -19,6 +19,7 @@
*/
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/system.h>
......
arch/mips/vr41xx/common/siu.c
View file @ e36f561a
......@@ -22,6 +22,7 @@
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/irq.h>
#include <asm/cpu.h>
#include <asm/vr41xx/siu.h>
......
arch/mn10300/include/asm/irqflags.h 0 → 100644
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arch/mn10300/include/asm/system.h
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arch/mn10300/kernel/entry.S
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arch/parisc/include/asm/irqflags.h 0 → 100644
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arch/parisc/include/asm/system.h
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arch/powerpc/include/asm/hw_irq.h
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arch/powerpc/include/asm/irqflags.h
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arch/powerpc/kernel/exceptions-64s.S
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arch/powerpc/kernel/irq.c
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arch/s390/include/asm/irqflags.h
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arch/s390/include/asm/system.h
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arch/s390/kernel/mem_detect.c
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arch/s390/mm/init.c
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arch/s390/mm/maccess.c
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arch/score/include/asm/irqflags.h
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arch/sh/include/asm/irqflags.h
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arch/sh/include/asm/syscalls_32.h
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arch/sh/kernel/irq_32.c
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arch/sparc/include/asm/irqflags_32.h
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arch/sparc/include/asm/irqflags_64.h
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arch/sparc/kernel/irq_32.c
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arch/sparc/prom/p1275.c
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arch/tile/include/asm/irqflags.h
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arch/x86/include/asm/irqflags.h
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arch/x86/include/asm/paravirt.h
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arch/x86/xen/spinlock.c
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arch/xtensa/include/asm/irqflags.h 0 → 100644
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arch/xtensa/include/asm/system.h
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crypto/des_generic.c
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drivers/net/bfin_mac.c
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drivers/net/smc91x.c
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drivers/s390/char/sclp.c
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drivers/vlynq/vlynq.c
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drivers/watchdog/octeon-wdt-main.c
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include/asm-generic/atomic.h
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include/asm-generic/cmpxchg-local.h
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include/asm-generic/irqflags.h
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include/linux/hardirq.h
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include/linux/irqflags.h
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include/linux/list.h
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include/linux/spinlock.h
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