Commit e47cb97f authored by Geert Uytterhoeven's avatar Geert Uytterhoeven

ARM: dts: r8a7740: Add missing extal2 to CPG node

The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.

This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.

Fixes: d9ffd583 ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200508095918.6061-1-geert+renesas@glider.be
parent b704fc1d
...@@ -479,7 +479,7 @@ fsibck_clk: fsibck { ...@@ -479,7 +479,7 @@ fsibck_clk: fsibck {
cpg_clocks: cpg_clocks@e6150000 { cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7740-cpg-clocks"; compatible = "renesas,r8a7740-cpg-clocks";
reg = <0xe6150000 0x10000>; reg = <0xe6150000 0x10000>;
clocks = <&extal1_clk>, <&extalr_clk>; clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "system", "pllc0", "pllc1", clock-output-names = "system", "pllc0", "pllc1",
"pllc2", "r", "pllc2", "r",
......
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