Commit e4b8d0b7 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Kleber Sacilotto de Souza

pinctrl: sh-pfc: sh7734: Add missing IPSR11 field

BugLink: https://bugs.launchpad.net/bugs/1864773

[ Upstream commit 94482af7 ]

The Peripheral Function Select Register 11 contains 3 reserved bits and
15 variable-width fields, but the variable field descriptor does not
contain the 3-bit field IP11[25:23].

Fixes: 856cb4bb ("sh: Add support pinmux for SH7734")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarKhalid Elmously <khalid.elmously@canonical.com>
Signed-off-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
parent 64f4acd2
...@@ -2242,7 +2242,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { ...@@ -2242,7 +2242,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCD_DATA15_B, 0, 0, 0 } FN_LCD_DATA15_B, 0, 0, 0 }
}, },
{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32, { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) { 3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
/* IP11_31_29 [3] */ /* IP11_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_28 [1] */ /* IP11_28 [1] */
......
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