Commit e56700b8 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Tony Lindgren

ARM: dts: dra7xx: Correct mcasp8_ahclkx_mux name

rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for the unit offsets]
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 42b2274d
......@@ -1856,7 +1856,7 @@ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
reg = <0x1908>;
};
mcasp8_ahclk_mux: mcasp8_ahclk_mux@1890 {
mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......
......@@ -223,7 +223,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
......
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