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Commit e5e95a76 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/mpeg: switch to instanced constructor 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent aba5e97b
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Showing with 57 additions and 60 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file @ e5e95a76
......@@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_engine *mpeg;
struct nvkm_engine *msenc;
struct nvkm_engine *mspdec;
struct nvkm_engine *msppp;
......@@ -113,7 +112,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
......
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View file @ e5e95a76
......@@ -53,12 +53,8 @@ int nvkm_engine_ctor_(const struct nvkm_engine_func *, bool old, struct nvkm_dev
#define nvkm_engine_ctor_n(f,d,t,i,e,s) nvkm_engine_ctor_((f), false, (d), (t), (i), (e), (s))
#define nvkm_engine_ctor__(_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define nvkm_engine_ctor(A...) nvkm_engine_ctor__(A, nvkm_engine_ctor_n, nvkm_engine_ctor_o)(A)
int nvkm_engine_new__(const struct nvkm_engine_func *, bool old, struct nvkm_device *,
int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *,
enum nvkm_subdev_type, int, bool enable, struct nvkm_engine **);
#define nvkm_engine_new__o(f,d,i, e,s) nvkm_engine_new__((f), true, (d), (i), -1 , (e), (s))
#define nvkm_engine_new__n(f,d,t,i,e,s) nvkm_engine_new__((f), false, (d), (t), (i), (e), (s))
#define nvkm_engine_new___(_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define nvkm_engine_new_(A...) nvkm_engine_new___(A, nvkm_engine_new__n, nvkm_engine_new__o)(A)
struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *);
void nvkm_engine_unref(struct nvkm_engine **);
......
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View file @ e5e95a76
......@@ -34,4 +34,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_FIFO , struct nvkm_fifo , fifo)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_GR , struct nvkm_gr , gr)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_IFB , struct nvkm_engine , ifb)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_ME , struct nvkm_engine , me)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MPEG , struct nvkm_engine , mpeg)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
View file @ e5e95a76
......@@ -2,9 +2,9 @@
#ifndef __NVKM_MPEG_H__
#define __NVKM_MPEG_H__
#include <core/engine.h>
int nv31_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv40_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv44_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv50_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int g84_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv31_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int nv40_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int nv44_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int nv50_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int g84_mpeg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/nvkm/core/engine.c
View file @ e5e95a76
......@@ -194,11 +194,11 @@ nvkm_engine_ctor_(const struct nvkm_engine_func *func, bool old, struct nvkm_dev
}
int
nvkm_engine_new__(const struct nvkm_engine_func *func, bool old, struct nvkm_device *device,
nvkm_engine_new_(const struct nvkm_engine_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, bool enable,
struct nvkm_engine **pengine)
{
if (!(*pengine = kzalloc(sizeof(**pengine), GFP_KERNEL)))
return -ENOMEM;
return nvkm_engine_ctor_(func, old, device, type, inst, enable, *pengine);
return nvkm_engine_ctor(func, device, type, inst, enable, *pengine);
}
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View file @ e5e95a76
......@@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_MPEG ] = "mpeg",
[NVKM_ENGINE_MSENC ] = "msenc",
[NVKM_ENGINE_MSPDEC ] = "mspdec",
[NVKM_ENGINE_MSPPP ] = "msppp",
......
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @ e5e95a76
......@@ -397,7 +397,7 @@ nv31_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = { 0x00000001, nv30_gr_new },
.mpeg = nv31_mpeg_new,
.mpeg = { 0x00000001, nv31_mpeg_new },
.sw = nv10_sw_new,
};
......@@ -420,7 +420,7 @@ nv34_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = { 0x00000001, nv34_gr_new },
.mpeg = nv31_mpeg_new,
.mpeg = { 0x00000001, nv31_mpeg_new },
.sw = nv10_sw_new,
};
......@@ -465,7 +465,7 @@ nv36_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = { 0x00000001, nv35_gr_new },
.mpeg = nv31_mpeg_new,
.mpeg = { 0x00000001, nv31_mpeg_new },
.sw = nv10_sw_new,
};
......@@ -490,7 +490,7 @@ nv40_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -516,7 +516,7 @@ nv41_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -542,7 +542,7 @@ nv42_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -568,7 +568,7 @@ nv43_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -594,7 +594,7 @@ nv44_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -620,7 +620,7 @@ nv45_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -646,7 +646,7 @@ nv46_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -672,7 +672,7 @@ nv47_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -698,7 +698,7 @@ nv49_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -724,7 +724,7 @@ nv4a_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -750,7 +750,7 @@ nv4b_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -776,7 +776,7 @@ nv4c_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -802,7 +802,7 @@ nv4e_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -831,7 +831,7 @@ nv50_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, nv50_fifo_new },
.gr = { 0x00000001, nv50_gr_new },
.mpeg = nv50_mpeg_new,
.mpeg = { 0x00000001, nv50_mpeg_new },
.pm = nv50_pm_new,
.sw = nv50_sw_new,
};
......@@ -857,7 +857,7 @@ nv63_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -883,7 +883,7 @@ nv67_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -909,7 +909,7 @@ nv68_chipset = {
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -940,7 +940,7 @@ nv84_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
......@@ -972,7 +972,7 @@ nv86_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
......@@ -1004,7 +1004,7 @@ nv92_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
......@@ -1036,7 +1036,7 @@ nv94_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
......@@ -1068,7 +1068,7 @@ nv96_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
......@@ -1132,7 +1132,7 @@ nva0_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt200_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = gt200_pm_new,
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
......@@ -1164,7 +1164,7 @@ nva3_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt215_gr_new },
.mpeg = g84_mpeg_new,
.mpeg = { 0x00000001, g84_mpeg_new },
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
......@@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_MPEG , mpeg);
_(NVKM_ENGINE_MSENC , msenc);
_(NVKM_ENGINE_MSPDEC , mspdec);
_(NVKM_ENGINE_MSPPP , msppp);
......
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
View file @ e5e95a76
......@@ -37,7 +37,8 @@ g84_mpeg = {
};
int
g84_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
g84_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nvkm_engine_new_(&g84_mpeg, device, index, true, pmpeg);
return nvkm_engine_new_(&g84_mpeg, device, type, inst, true, pmpeg);
}
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
View file @ e5e95a76
......@@ -274,7 +274,7 @@ nv31_mpeg_ = {
int
nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device,
int index, struct nvkm_engine **pmpeg)
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pmpeg)
{
struct nv31_mpeg *mpeg;
......@@ -283,8 +283,7 @@ nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device,
mpeg->func = func;
*pmpeg = &mpeg->engine;
return nvkm_engine_ctor(&nv31_mpeg_, device, index,
true, &mpeg->engine);
return nvkm_engine_ctor(&nv31_mpeg_, device, type, inst, true, &mpeg->engine);
}
static const struct nv31_mpeg_func
......@@ -293,7 +292,8 @@ nv31_mpeg = {
};
int
nv31_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
nv31_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nv31_mpeg_new_(&nv31_mpeg, device, index, pmpeg);
return nv31_mpeg_new_(&nv31_mpeg, device, type, inst, pmpeg);
}
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
View file @ e5e95a76
......@@ -11,8 +11,8 @@ struct nv31_mpeg {
struct nv31_mpeg_chan *chan;
};
int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *,
int index, struct nvkm_engine **);
int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_engine **);
struct nv31_mpeg_func {
bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data);
......
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
View file @ e5e95a76
......@@ -76,7 +76,8 @@ nv40_mpeg = {
};
int
nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
nv40_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg);
return nv31_mpeg_new_(&nv40_mpeg, device, type, inst, pmpeg);
}
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
View file @ e5e95a76
......@@ -203,7 +203,8 @@ nv44_mpeg = {
};
int
nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
nv44_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
struct nv44_mpeg *mpeg;
......@@ -212,5 +213,5 @@ nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
INIT_LIST_HEAD(&mpeg->chan);
*pmpeg = &mpeg->engine;
return nvkm_engine_ctor(&nv44_mpeg, device, index, true, &mpeg->engine);
return nvkm_engine_ctor(&nv44_mpeg, device, type, inst, true, &mpeg->engine);
}
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
View file @ e5e95a76
......@@ -129,7 +129,8 @@ nv50_mpeg = {
};
int
nv50_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
nv50_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nvkm_engine_new_(&nv50_mpeg, device, index, true, pmpeg);
return nvkm_engine_new_(&nv50_mpeg, device, type, inst, true, pmpeg);
}
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
View file @ e5e95a76
......@@ -35,7 +35,7 @@ g84_devinit_disable(struct nvkm_devinit *init)
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVKM_ENGINE_MPEG);
nvkm_subdev_disable(device, NVKM_ENGINE_MPEG, 0);
nvkm_subdev_disable(device, NVKM_ENGINE_VP, 0);
nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0);
nvkm_subdev_disable(device, NVKM_ENGINE_CIPHER, 0);
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
View file @ e5e95a76
......@@ -85,7 +85,7 @@ nv50_devinit_disable(struct nvkm_devinit *init)
u64 disable = 0ULL;
if (!(r001540 & 0x40000000))
disable |= (1ULL << NVKM_ENGINE_MPEG);
nvkm_subdev_disable(device, NVKM_ENGINE_MPEG, 0);
return disable;
}
......
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