Commit e60e2a29 authored by Neil Armstrong's avatar Neil Armstrong Committed by Greg Kroah-Hartman

soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask

[ Upstream commit 2fe3b4bb ]

The register bitmask to power on/off the VPU memories was incorectly set
to 0x2 instead of 0x3. While still working, let's use the recommended
vendor value instead.

Fixes: 75fcb5ca ("soc: amlogic: add Meson GX VPU Domains driver")
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 1159872c
...@@ -54,12 +54,12 @@ static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd) ...@@ -54,12 +54,12 @@ static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
/* Power Down Memories */ /* Power Down Memories */
for (i = 0; i < 32; i += 2) { for (i = 0; i < 32; i += 2) {
regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
0x2 << i, 0x3 << i); 0x3 << i, 0x3 << i);
udelay(5); udelay(5);
} }
for (i = 0; i < 32; i += 2) { for (i = 0; i < 32; i += 2) {
regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
0x2 << i, 0x3 << i); 0x3 << i, 0x3 << i);
udelay(5); udelay(5);
} }
for (i = 8; i < 16; i++) { for (i = 8; i < 16; i++) {
...@@ -108,13 +108,13 @@ static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd) ...@@ -108,13 +108,13 @@ static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
/* Power Up Memories */ /* Power Up Memories */
for (i = 0; i < 32; i += 2) { for (i = 0; i < 32; i += 2) {
regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0, regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
0x2 << i, 0); 0x3 << i, 0);
udelay(5); udelay(5);
} }
for (i = 0; i < 32; i += 2) { for (i = 0; i < 32; i += 2) {
regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1, regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
0x2 << i, 0); 0x3 << i, 0);
udelay(5); udelay(5);
} }
......
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