Commit e614a121 authored by Peter Griffin's avatar Peter Griffin Committed by Patrice Chotard

ARM: dts: stih407-clocks: Identify critical clocks

Lots of platforms contain clocks which if turned off would prove fatal.
The only way to recover is to restart the board(s).  This driver takes
references to clocks which are required to be always-on.  The Common
Clk Framework will then take references to them.  This way they will
not be turned off during the clk_disabled_unused() procedure.

In this patch we are identifying clocks, which if gated would render
the STiH407 development board unserviceable.
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Acked-by: default avatarPatrice Chotard <patrice.chotard@st.com>
parent fd166a3e
......@@ -101,6 +101,7 @@ clk_s_a0_pll: clk-s-a0-pll {
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
......@@ -112,6 +113,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
<&clk_sysin>;
clock-output-names = "clk-ic-lmi0";
clock-critical = <CLK_IC_LMI0>;
};
};
......@@ -126,6 +128,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@09103000 {
......@@ -139,6 +142,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
......@@ -194,6 +198,12 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp";
clock-critical = <CLK_PROC_STFE>,
<CLK_ICN_CPU>,
<CLK_TX_ICN_DMU>,
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
};
};
......
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