Skip to content

L
linux
Commit e777f8c8 authored by Linus Walleij's avatar Linus Walleij
Browse files
Options

Merge tag 'renesas-pinctrl-for-v5.10-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.10

  - Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
  - Three more conversion of DT bindings to json-schema,
  - Group all Renesas pinctrl drivers and improve visual Kconfig
    structure,
  - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
  - Minor fixes and improvements.
parents 84f28fc3 540d9757
Hide whitespace changes
Inline Side-by-side
Showing with 811 additions and 711 deletions
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt deleted 100644 → 0
View file @ 84f28fc3
* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
R8A73A4 and R8A7740 it also acts as a GPIO controller.
Pin Control
-----------
Required Properties:
- compatible: should be one of the following.
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
- "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
- "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
controller hardware module.
Optional properties:
- #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
otherwise. Should be 3.
- interrupts-extended: Specify the interrupts associated with external
IRQ pins. This property is mandatory when the PFC handles GPIOs and
forbidden otherwise. When specified, it must contain one interrupt per
external IRQ, sorted by external IRQ number.
The PFC node also acts as a container for pin configuration nodes. Please refer
to pinctrl-bindings.txt in this directory for the definition of the term "pin
configuration node" and for the common pinctrl bindings used by client devices.
Each pin configuration node represents a desired configuration for a pin, a
pin group, or a list of pins or pin groups. The configuration can include the
function to select on those pin(s) and pin configuration parameters (such as
pull-up and pull-down).
Pin configuration nodes contain pin configuration properties, either directly
or grouped in child subnodes. Both pin muxing and configuration parameters can
be grouped in that way and referenced as a single pin configuration node by
client devices.
A configuration node or subnode must reference at least one pin (through the
pins or pin groups properties) and contain at least a function or one
configuration parameter. When the function is present only pin groups can be
used to reference pins.
All pin configuration nodes and subnodes names are ignored. All of those nodes
are parsed through phandles and processed purely based on their content.
Pin Configuration Node Properties:
- pins : An array of strings, each string containing the name of a pin.
- groups : An array of strings, each string containing the name of a pin
group.
- function: A string containing the name of the function to mux to the pin
group(s) specified by the groups property.
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
(drivers/pinctrl/sh-pfc/pfc-*.c)
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
pins that have a configurable I/O voltage, the power-source value should be the
nominal I/O voltage in millivolts.
GPIO
----
On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node.
Required Properties:
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
The syntax of the gpio specifier used by client nodes should be the following
with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
for documentation of the GPIO device tree bindings on those platforms.
Examples
--------
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
gpio-controller;
#gpio-cells = <2>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
};
Example 2: A GPIO LED node that references a GPIO
#include <dt-bindings/gpio/gpio.h>
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
};
};
Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
for the MMCIF and SCIFA4 devices
&pfc {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
mmcif_pins: mmcif {
mux {
groups = "mmc0_data8_0", "mmc0_ctrl_0";
function = "mmc0";
};
cfg {
groups = "mmc0_data8_0";
pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: scifa4 {
groups = "scifa4_data", "scifa4_ctrl";
function = "scifa4";
};
};
Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
};
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml 0 → 100644
View file @ e777f8c8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Pin Function Controller (PFC) is a Pin Mux/Config controller.
On SH/R-Mobile SoCs it also acts as a GPIO controller.
properties:
compatible:
enum:
- renesas,pfc-emev2 # EMMA Mobile EV2
- renesas,pfc-r8a73a4 # R-Mobile APE6
- renesas,pfc-r8a7740 # R-Mobile A1
- renesas,pfc-r8a7742 # RZ/G1H
- renesas,pfc-r8a7743 # RZ/G1M
- renesas,pfc-r8a7744 # RZ/G1N
- renesas,pfc-r8a7745 # RZ/G1E
- renesas,pfc-r8a77470 # RZ/G1C
- renesas,pfc-r8a774a1 # RZ/G2M
- renesas,pfc-r8a774b1 # RZ/G2N
- renesas,pfc-r8a774c0 # RZ/G2E
- renesas,pfc-r8a774e1 # RZ/G2H
- renesas,pfc-r8a7778 # R-Car M1
- renesas,pfc-r8a7779 # R-Car H1
- renesas,pfc-r8a7790 # R-Car H2
- renesas,pfc-r8a7791 # R-Car M2-W
- renesas,pfc-r8a7792 # R-Car V2H
- renesas,pfc-r8a7793 # R-Car M2-N
- renesas,pfc-r8a7794 # R-Car E2
- renesas,pfc-r8a7795 # R-Car H3
- renesas,pfc-r8a7796 # R-Car M3-W
- renesas,pfc-r8a77961 # R-Car M3-W+
- renesas,pfc-r8a77965 # R-Car M3-N
- renesas,pfc-r8a77970 # R-Car V3M
- renesas,pfc-r8a77980 # R-Car V3H
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
minItems: 1
maxItems: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
minItems: 1
maxItems: 16
interrupts-extended:
minItems: 32
maxItems: 64
description:
Specify the interrupts associated with external IRQ pins on SoCs where
the PFC acts as a GPIO controller. It must contain one interrupt per
external IRQ, sorted by external IRQ number.
power-domains:
maxItems: 1
required:
- compatible
- reg
if:
properties:
compatible:
items:
enum:
- renesas,pfc-r8a73a4
- renesas,pfc-r8a7740
- renesas,pfc-sh73a0
then:
required:
- interrupts-extended
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- power-domains
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
function: true
groups: true
pins: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values
power-source:
enum: [ 1800, 3300 ]
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 212>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
power-domains = <&pd_c5>;
lcd0_mux {
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
gpios = <176 0>;
output-high;
};
};
- |
pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0xe6060000 0x50c>;
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",
"PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",
"PIN_AVB_TD3";
drive-strength = <12>;
};
};
keys_pins: keys {
pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";
bias-pull-up;
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt deleted 100644 → 0
View file @ 84f28fc3
Renesas RZ/A1 combined Pin and GPIO controller
The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
named "Ports" in the hardware reference manual.
Pin multiplexing and GPIO configuration is performed on a per-pin basis
writing configuration values to per-port register sets.
Each "port" features up to 16 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
Pin controller node
-------------------
Required properties:
- compatible: should be:
- "renesas,r7s72100-ports": for RZ/A1H
- "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
- "renesas,r7s72102-ports": for RZ/A1L
- reg
address base and length of the memory area where the pin controller
hardware is mapped to.
Example:
Pin controller node for RZ/A1H SoC (r7s72100)
pinctrl: pin-controller@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function or a GPIO controller alternatively.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
A few alternate function require special pin configuration flags to be
supplied along with the alternate function configuration number.
The hardware reference manual specifies when a pin function requires
"software IO driven" mode to be specified. To do so use the generic
properties from the <include/linux/pinctrl/pinconf_generic.h> header file
to instruct the pin controller to perform the desired pin configuration
operation.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the second format when pins part of the same logical group need to have
different generic pin configuration flags applied.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function identifier
are provided by the pin controller header file at:
<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
Optional generic properties:
- input-enable:
enable input bufer for pins requiring software driven IO input
operations.
- output-high:
enable output buffer for pins requiring software driven IO output
operations. output-low can be used alternatively, as line value is
ignored by the driver.
The hardware reference manual specifies when a pin has to be configured to
work in bi-directional mode and when the IO direction has to be specified
by software. Bi-directional pins are managed by the pin controller driver
internally, while software driven IO direction has to be explicitly
selected when multiple options are available.
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
};
Pin #0 on port #3 is configured as alternate function #6.
Pin #2 on port #3 is configured as alternate function #4.
Example 2:
I2c master: both SDA and SCL pins need bi-directional operations
&pinctrl {
i2c2_pins: i2c2 {
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
};
Pin #4 on port #1 is configured as alternate function #1.
Pin #5 on port #1 is configured as alternate function #1.
Both need to work in bi-directional mode, the driver manages this internally.
Example 3:
Multi-function timer input and output compare pins.
Configure TIOC0A as software driven input and TIOC0B as software driven
output.
&pinctrl {
tioc0_pins: tioc0 {
tioc0_input_pins {
pinumx = <RZA1_PINMUX(4, 0, 2)>;
input-enable;
};
tioc0_output_pins {
pinmux = <RZA1_PINMUX(4, 1, 1)>;
output-enable;
};
};
};
&tioc0 {
...
pinctrl-0 = <&tioc0_pins>;
...
};
Pin #0 on port #4 is configured as alternate function #2 with IO direction
specified by software as input.
Pin #1 on port #4 is configured as alternate function #1 with IO direction
specified by software as output.
- GPIO controller sub-nodes:
Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
Different SoCs have different numbers of available pins per port, but
generally speaking, each of them can be configured in GPIO ("port") mode
on this hardware.
Describe GPIO controllers using sub-nodes with the following properties.
Required properties:
- gpio-controller
empty property as defined by the GPIO bindings documentation.
- #gpio-cells
number of cells required to identify and configure a GPIO.
Shall be 2.
- gpio-ranges
Describes a GPIO controller specifying its specific pin base, the pin
base in the global pin numbering space, and the number of controlled
pins, as defined by the GPIO bindings documentation. Refer to
Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
description.
Example:
A GPIO controller node, controlling 16 pins indexed from 0.
The GPIO controller base in the global pin indexing space is pin 48, thus
pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
indexing space.
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
A device node willing to use pins controlled by this GPIO controller, shall
refer to it as follows:
led1 {
gpios = <&port3 10 GPIO_ACTIVE_LOW>;
};
Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml 0 → 100644
View file @ e777f8c8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/A1 combined Pin and GPIO controller
maintainers:
- Jacopo Mondi <jacopo+renesas@jmondi.org>
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
controller, named "Ports" in the hardware reference manual.
Pin multiplexing and GPIO configuration is performed on a per-pin basis
writing configuration values to per-port register sets.
Each "port" features up to 16 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
oneOf:
- const: renesas,r7s72100-ports # RZ/A1H
- items:
- const: renesas,r7s72101-ports # RZ/A1M
- const: renesas,r7s72100-ports # fallback
- const: renesas,r7s72102-ports # RZ/A1L
reg:
maxItems: 1
required:
- compatible
- reg
patternProperties:
"^gpio-[0-9]*$":
type: object
description:
Each port of the r7s72100 pin controller hardware is itself a GPIO
controller.
Different SoCs have different numbers of available pins per port, but
generally speaking, each of them can be configured in GPIO ("port") mode
on this hardware.
Describe GPIO controllers using sub-nodes with the following properties.
properties:
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
required:
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
A few alternate function require special pin configuration flags to be
supplied along with the alternate function configuration number.
The hardware reference manual specifies when a pin function requires
"software IO driven" mode to be specified. To do so use the generic
properties from the <include/linux/pinctrl/pinconf_generic.h> header
file to instruct the pin controller to perform the desired pin
configuration operation.
The hardware reference manual specifies when a pin has to be configured
to work in bi-directional mode and when the IO direction has to be
specified by software. Bi-directional pins must be managed by the pin
controller driver internally, while software driven IO direction has to
be explicitly selected when multiple options are available.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function
identifier are provided by the pin controller header file at:
<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
phandle: true
input-enable: true
output-enable: true
required:
- pinmux
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
/*
* A GPIO controller node, controlling 16 pins indexed from 0.
* The GPIO controller base in the global pin indexing space is pin
* 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
* in the global pin indexing space.
*/
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
* Pin #0 on port #3 is configured as alternate function #6.
* Pin #2 on port #3 is configured as alternate function #4.
*/
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
/*
* I2c master: both SDA and SCL pins need bi-directional operations
* Pin #4 on port #1 is configured as alternate function #1.
* Pin #5 on port #1 is configured as alternate function #1.
* Both need to work in bi-directional mode, the driver must manage
* this internally.
*/
i2c2_pins: i2c2 {
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
/*
* Multi-function timer input and output compare pins.
*/
tioc0_pins: tioc0 {
/*
* Configure TIOC0A as software driven input
* Pin #0 on port #4 is configured as alternate function #2
* with IO direction specified by software as input.
*/
tioc0_input_pins {
pinmux = <RZA1_PINMUX(4, 0, 2)>;
input-enable;
};
/*
* Configure TIOC0B as software driven output
* Pin #1 on port #4 is configured as alternate function #1
* with IO direction specified by software as output.
*/
tioc0_output_pins {
pinmux = <RZA1_PINMUX(4, 1, 1)>;
output-enable;
};
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
View file @ e777f8c8
......@@ -84,7 +84,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
pinctrl: pin-controller@fcffe000 {
pinctrl: pinctrl@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
......
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt deleted 100644 → 0
View file @ 84f28fc3
Renesas RZ/N1 SoC Pinctrl node description.
Pin controller node
-------------------
Required properties:
- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
strings must be one of:
"renesas,r9a06g032-pinctrl" for RZ/N1D
"renesas,r9a06g033-pinctrl" for RZ/N1S
- reg: Address base and length of the memory area where the pin controller
hardware is mapped to.
- clocks: phandle for the clock, see the description of clock-names below.
- clock-names: Contains the name of the clock:
"bus", the bus clock, sometimes described as pclk, for register accesses.
Example:
pinctrl: pin-controller@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
node-3 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the latter two formats when pins part of the same logical group need to
have different generic pin configuration flags applied. Note that the generic
pinconfig in node-3 does not apply to the sub-nodes.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is
one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1 and
Level 2 numbers that are detailed in the hardware reference manual into a
single number. The identifiers for Level 2 are simply offset by 10.
Additional identifiers are provided to specify the MDIO source peripheral.
Optional generic pinconf properties:
- bias-disable - disable any pin bias
- bias-pull-up - pull up the pin with 50 KOhm
- bias-pull-down - pull down the pin with 50 KOhm
- bias-high-impedance - high impedance mode
- drive-strength - sink or source at most 4, 6, 8 or 12 mA
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
};
Example 2:
Here we set the pull up on the RXD pin of the UART.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml 0 → 100644
View file @ e777f8c8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 Pin Controller
maintainers:
- Gareth Williams <gareth.williams.jx@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-pinctrl # RZ/N1D
- renesas,r9a06g033-pinctrl # RZ/N1S
- const: renesas,rzn1-pinctrl # Generic RZ/N1
reg:
items:
- description: GPIO Multiplexing Level1 Register Block
- description: GPIO Multiplexing Level2 Register Block
clocks:
maxItems: 1
clock-names:
const: bus
description:
The bus clock, sometimes described as pclk, for register accesses.
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and
MUX_FUNC is one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1
and Level 2 numbers that are detailed in the hardware reference
manual into a single number. The identifiers for Level 2 are simply
offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral.
phandle: true
bias-disable: true
bias-pull-up:
description: Pull up the pin with 50 kOhm
bias-pull-down:
description: Pull down the pin with 50 kOhm
bias-high-impedance: true
drive-strength:
enum: [ 4, 6, 8, 12 ]
required:
- pinmux
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
*/
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
/*
* Set the pull-up on the RXD pin of the UART.
*/
pins_uart0_alt: pins_uart0_alt {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
bias-pull-up;
};
};
};
MAINTAINERS
View file @ e777f8c8
......@@ -13688,10 +13688,9 @@ PIN CONTROLLER - RENESAS
M: Geert Uytterhoeven <geert+renesas@glider.be>
L: linux-renesas-soc@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
F: Documentation/devicetree/bindings/pinctrl/renesas,*
F: drivers/pinctrl/pinctrl-rz*
F: drivers/pinctrl/sh-pfc/
F: drivers/pinctrl/renesas/
PIN CONTROLLER - SAMSUNG
M: Tomasz Figa <tomasz.figa@gmail.com>
......
drivers/pinctrl/Kconfig
View file @ e777f8c8
......@@ -215,38 +215,6 @@ config PINCTRL_ROCKCHIP
select MFD_SYSCON
select OF_GPIO
config PINCTRL_RZA1
bool "Renesas RZ/A1 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S72100 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "Renesas RZ/A2 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
depends on ARCH_RZN1 || COMPILE_TEST
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/N1 devices.
config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
depends on OF
......@@ -417,8 +385,8 @@ source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
......
drivers/pinctrl/Makefile
View file @ e777f8c8
......@@ -30,9 +30,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
......@@ -62,8 +59,8 @@ obj-y += nomadik/
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
......
drivers/pinctrl/sh-pfc/Kconfig → drivers/pinctrl/renesas/Kconfig
View file @ e777f8c8
......@@ -3,12 +3,11 @@
# Renesas SH and SH Mobile PINCTRL drivers
#
config PINCTRL_SH_PFC
menu "Renesas pinctrl drivers"
config PINCTRL_RENESAS
bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
default y if ARCH_RENESAS || SUPERH
select PINMUX
select PINCONF
select GENERIC_PINCONF
select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
......@@ -53,153 +52,220 @@ config PINCTRL_SH_PFC
help
This enables pin control drivers for Renesas SuperH and ARM platforms
config PINCTRL_SH_PFC
bool
select GENERIC_PINCONF
select PINMUX
select PINCONF
help
This enables common pin control functionality for EMMA Mobile, R-Car,
R-Mobile, RZ/G, SH, and SH-Mobile platforms.
config PINCTRL_SH_PFC_GPIO
select GPIOLIB
bool
select GPIOLIB
select PINCTRL_SH_PFC
help
This enables pin control and GPIO drivers for SH/SH Mobile platforms
config PINCTRL_SH_FUNC_GPIO
select PINCTRL_SH_PFC_GPIO
bool
select PINCTRL_SH_PFC_GPIO
help
This enables legacy function GPIOs for SH platforms
config PINCTRL_PFC_EMEV2
bool "Emma Mobile AV2 pin control support" if COMPILE_TEST
bool "pin control support for Emma Mobile EV2" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A73A4
bool "R-Mobile APE6 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A77995
bool "pin control support for R-Car D3" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7740
bool "R-Mobile A1 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7794
bool "pin control support for R-Car E2" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7742
bool "RZ/G1H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77990
bool "pin control support for R-Car E3" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7743
bool "RZ/G1M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7779
bool "pin control support for R-Car H1" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7744
bool "RZ/G1N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7790
bool "pin control support for R-Car H2" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7745
bool "RZ/G1E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77950
bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77470
bool "RZ/G1C pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77951
bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774A1
bool "RZ/G2M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7778
bool "pin control support for R-Car M1A" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774B1
bool "RZ/G2N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7793
bool "pin control support for R-Car M2-N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774C0
bool "RZ/G2E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7791
bool "pin control support for R-Car M2-W" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774E1
bool "RZ/G2H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77965
bool "pin control support for R-Car M3-N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7778
bool "R-Car M1A pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77960
bool "pin control support for R-Car M3-W" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7779
bool "R-Car H1 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77961
bool "pin control support for R-Car M3-W+" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7790
bool "R-Car H2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7792
bool "pin control support for R-Car V2H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7791
bool "R-Car M2-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77980
bool "pin control support for R-Car V3H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7792
bool "R-Car V2H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77970
bool "pin control support for R-Car V3M" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7793
bool "R-Car M2-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7740
bool "pin control support for R-Mobile A1" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7794
bool "R-Car E2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A73A4
bool "pin control support for R-Mobile APE6" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A77950
bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST
config PINCTRL_RZA1
bool "pin control support for RZ/A1"
depends on OF
depends on ARCH_R7S72100 || COMPILE_TEST
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "pin control support for RZ/A2"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_PFC_R8A77951
bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77470
bool "pin control support for RZ/G1C" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77960
bool "R-Car M3-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7745
bool "pin control support for RZ/G1E" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77961
bool "R-Car M3-W+ pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7742
bool "pin control support for RZ/G1H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77965
bool "R-Car M3-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7743
bool "pin control support for RZ/G1M" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77970
bool "R-Car V3M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7744
bool "pin control support for RZ/G1N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77980
bool "R-Car V3H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774C0
bool "pin control support for RZ/G2E" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77990
bool "R-Car E3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774E1
bool "pin control support for RZ/G2H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77995
bool "R-Car D3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774A1
bool "pin control support for RZ/G2M" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774B1
bool "pin control support for RZ/G2N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_RZN1
bool "pin control support for RZ/N1"
depends on OF
depends on ARCH_RZN1 || COMPILE_TEST
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/N1 devices.
config PINCTRL_PFC_SH7203
bool "SH7203 pin control support" if COMPILE_TEST
bool "pin control support for SH7203" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7264
bool "SH7264 pin control support" if COMPILE_TEST
bool "pin control support for SH7264" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7269
bool "SH7269 pin control support" if COMPILE_TEST
bool "pin control support for SH7269" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH73A0
bool "SH-Mobile AG5 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7720
bool "SH7720 pin control support" if COMPILE_TEST
bool "pin control support for SH7720" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7722
bool "SH7722 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7723
bool "SH-Mobile R2 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7724
bool "SH-Mobile R2R pin control support" if COMPILE_TEST
bool "pin control support for SH7722" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7734
bool "SH7734 pin control support" if COMPILE_TEST
bool "pin control support for SH7734" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7757
bool "SH7757 pin control support" if COMPILE_TEST
bool "pin control support for SH7757" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7785
bool "SH7785 pin control support" if COMPILE_TEST
bool "pin control support for SH7785" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7786
bool "SH7786 pin control support" if COMPILE_TEST
bool "pin control support for SH7786" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH73A0
bool "pin control support for SH-Mobile AG5" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7723
bool "pin control support for SH-Mobile R2" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7724
bool "pin control support for SH-Mobile R2R" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SHX3
bool "SH-X3 pin control support" if COMPILE_TEST
bool "pin control support for SH-X3" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
endmenu
drivers/pinctrl/sh-pfc/Makefile → drivers/pinctrl/renesas/Makefile
View file @ e777f8c8
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o
......@@ -43,6 +43,10 @@ obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o
obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a
......
drivers/pinctrl/sh-pfc/pfc-r8a7790.c → drivers/pinctrl/renesas/pfc-r8a7790.c
View file @ e777f8c8
......@@ -1871,6 +1871,86 @@ static const unsigned int avb_gmii_mux[] = {
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
/* - CAN0 ----------------------------------------------------------------- */
static const unsigned int can0_data_pins[] = {
/* CAN0 RX */
RCAR_GP_PIN(1, 17),
/* CAN0 TX */
RCAR_GP_PIN(1, 19),
};
static const unsigned int can0_data_mux[] = {
CAN0_RX_MARK,
CAN0_TX_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* CAN0 RXB */
RCAR_GP_PIN(4, 5),
/* CAN0 TXB */
RCAR_GP_PIN(4, 4),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_RX_B_MARK,
CAN0_TX_B_MARK,
};
static const unsigned int can0_data_c_pins[] = {
/* CAN0 RXC */
RCAR_GP_PIN(4, 26),
/* CAN0 TXC */
RCAR_GP_PIN(4, 23),
};
static const unsigned int can0_data_c_mux[] = {
CAN0_RX_C_MARK,
CAN0_TX_C_MARK,
};
static const unsigned int can0_data_d_pins[] = {
/* CAN0 RXD */
RCAR_GP_PIN(4, 26),
/* CAN0 TXD */
RCAR_GP_PIN(4, 18),
};
static const unsigned int can0_data_d_mux[] = {
CAN0_RX_D_MARK,
CAN0_TX_D_MARK,
};
/* - CAN1 ----------------------------------------------------------------- */
static const unsigned int can1_data_pins[] = {
/* CAN1 RX */
RCAR_GP_PIN(1, 22),
/* CAN1 TX */
RCAR_GP_PIN(1, 18),
};
static const unsigned int can1_data_mux[] = {
CAN1_RX_MARK,
CAN1_TX_MARK,
};
static const unsigned int can1_data_b_pins[] = {
/* CAN1 RXB */
RCAR_GP_PIN(4, 7),
/* CAN1 TXB */
RCAR_GP_PIN(4, 6),
};
static const unsigned int can1_data_b_mux[] = {
CAN1_RX_B_MARK,
CAN1_TX_B_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 21),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
static const unsigned int can_clk_b_pins[] = {
/* CLK */
RCAR_GP_PIN(4, 3),
};
static const unsigned int can_clk_b_mux[] = {
CAN_CLK_B_MARK,
};
/* - DU RGB ----------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
......@@ -3611,6 +3691,13 @@ static const unsigned int usb1_pins[] = {
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
static const unsigned int usb1_pwen_pins[] = {
/* PWEN */
RCAR_GP_PIN(5, 20),
};
static const unsigned int usb1_pwen_mux[] = {
USB1_PWEN_MARK,
};
/* - USB2 ------------------------------------------------------------------- */
static const unsigned int usb2_pins[] = {
/* PWEN, OVC */
......@@ -3939,7 +4026,7 @@ static const unsigned int vin3_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[289];
struct sh_pfc_pin_group common[298];
struct sh_pfc_pin_group automotive[1];
} pinmux_groups = {
.common = {
......@@ -3956,6 +4043,14 @@ static const struct {
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can0_data_c),
SH_PFC_PIN_GROUP(can0_data_d),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can1_data_b),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(can_clk_b),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
......@@ -4193,6 +4288,7 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb0_ovc_vbus),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb1_pwen),
SH_PFC_PIN_GROUP(usb2),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
......@@ -4257,6 +4353,23 @@ static const char * const avb_groups[] = {
"avb_gmii",
};
static const char * const can0_groups[] = {
"can0_data",
"can0_data_b",
"can0_data_c",
"can0_data_d",
};
static const char * const can1_groups[] = {
"can1_data",
"can1_data_b",
};
static const char * const can_clk_groups[] = {
"can_clk",
"can_clk_b",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
......@@ -4640,6 +4753,7 @@ static const char * const usb0_groups[] = {
static const char * const usb1_groups[] = {
"usb1",
"usb1_pwen",
};
static const char * const usb2_groups[] = {
......@@ -4697,13 +4811,16 @@ static const char * const vin3_groups[] = {
};
static const struct {
struct sh_pfc_function common[55];
struct sh_pfc_function common[58];
struct sh_pfc_function automotive[1];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(du2),
......
drivers/pinctrl/sh-pfc/pfc-r8a7796.c → drivers/pinctrl/renesas/pfc-r8a7796.c
View file @ e777f8c8
......@@ -4,7 +4,7 @@
*
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
......
drivers/pinctrl/sh-pfc/pfc-r8a77965.c → drivers/pinctrl/renesas/pfc-r8a77965.c
View file @ e777f8c8
......@@ -5,7 +5,7 @@
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
......
drivers/pinctrl/sh-pfc/pfc-r8a77970.c → drivers/pinctrl/renesas/pfc-r8a77970.c
View file @ e777f8c8
......@@ -5,7 +5,7 @@
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
......
drivers/pinctrl/sh-pfc/pfc-r8a77980.c → drivers/pinctrl/renesas/pfc-r8a77980.c
View file @ e777f8c8
......@@ -5,7 +5,7 @@
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
......
drivers/pinctrl/sh-pfc/pfc-r8a77990.c → drivers/pinctrl/renesas/pfc-r8a77990.c
View file @ e777f8c8
......@@ -4,7 +4,7 @@
*
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R8A7796 processor support - PFC hardware block.
*
......
drivers/pinctrl/sh-pfc/pfc-r8a77995.c → drivers/pinctrl/renesas/pfc-r8a77995.c
View file @ e777f8c8
......@@ -4,7 +4,7 @@
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
......
drivers/pinctrl/pinctrl-rza1.c → drivers/pinctrl/renesas/pinctrl-rza1.c
View file @ e777f8c8
......@@ -26,10 +26,10 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "devicetree.h"
#include "pinconf.h"
#include "pinmux.h"
#include "../core.h"
#include "../devicetree.h"
#include "../pinconf.h"
#include "../pinmux.h"
#define DRIVER_NAME "pinctrl-rza1"
......@@ -928,7 +928,8 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
case PIN_CONFIG_INPUT_ENABLE:
pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
break;
case PIN_CONFIG_OUTPUT:
case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
case PIN_CONFIG_OUTPUT_ENABLE:
pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
default:
break;
......
drivers/pinctrl/pinctrl-rza2.c → drivers/pinctrl/renesas/pinctrl-rza2.c
View file @ e777f8c8
......@@ -17,8 +17,8 @@
#include <linux/of_device.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinmux.h"
#include "../core.h"
#include "../pinmux.h"
#define DRIVER_NAME "pinctrl-rza2"
......
drivers/pinctrl/pinctrl-rzn1.c → drivers/pinctrl/renesas/pinctrl-rzn1.c
View file @ e777f8c8
......@@ -17,9 +17,9 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
/* Field positions and masks in the pinmux registers */
#define RZN1_L1_PIN_DRIVE_STRENGTH 10
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7