[PATCH] I2C: coding style updates for i2c-iop3xx driver

drivers/i2c/i2c-iop3xx.h

@@ -25,20 +25,20 @@
 /*
  * iop321 hardware bit definitions
  */
-#define IOP321_ICR_FAST_MODE  0x8000 /* 1=400kBps, 0=100kBps */
-#define IOP321_ICR_UNIT_RESET 0x4000 /* 1=RESET */
-#define IOP321_ICR_SADIE      0x2000 /* 1=Slave Detect Interrupt Enable */
-#define IOP321_ICR_ALDIE      0x1000 /* 1=Arb Loss Detect Interrupt Enable */
-#define IOP321_ICR_SSDIE      0x0800 /* 1=Slave STOP Detect Interrupt Enable */
-#define IOP321_ICR_BERRIE     0x0400 /* 1=Bus Error Interrupt Enable */
-#define IOP321_ICR_RXFULLIE   0x0200 /* 1=Receive Full Interrupt Enable */
-#define IOP321_ICR_TXEMPTYIE  0x0100 /* 1=Transmit Empty Interrupt Enable */
-#define IOP321_ICR_GCD        0x0080 /* 1=General Call Disable */
+#define IOP321_ICR_FAST_MODE	0x8000	/* 1=400kBps, 0=100kBps */
+#define IOP321_ICR_UNIT_RESET	0x4000	/* 1=RESET */
+#define IOP321_ICR_SADIE	0x2000	/* 1=Slave Detect Interrupt Enable */
+#define IOP321_ICR_ALDIE	0x1000	/* 1=Arb Loss Detect Interrupt Enable */
+#define IOP321_ICR_SSDIE	0x0800	/* 1=Slave STOP Detect Interrupt Enable */
+#define IOP321_ICR_BERRIE	0x0400	/* 1=Bus Error Interrupt Enable */
+#define IOP321_ICR_RXFULLIE	0x0200	/* 1=Receive Full Interrupt Enable */
+#define IOP321_ICR_TXEMPTYIE	0x0100	/* 1=Transmit Empty Interrupt Enable */
+#define IOP321_ICR_GCD		0x0080	/* 1=General Call Disable */
 /*
  * IOP321_ICR_GCD: 1 disables response as slave. "This bit must be set
  * when sending a master mode general call message from the I2C unit"
  */
-#define IOP321_ICR_UE         0x0040 /* 1=Unit Enable */
+#define IOP321_ICR_UE		0x0040	/* 1=Unit Enable */
 /*
  * "NOTE: To avoid I2C bus integrity problems, 
  * the user needs to ensure that the GPIO Output Data Register - 
@@ -46,56 +46,54 @@
  * the enable bit for that I2C serial port. 
  * The user prepares to enable I2C port 0 and 
  * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
- */                                     
-#define IOP321_ICR_SCLEN     0x0020 /* 1=SCL enable for master mode */
-#define IOP321_ICR_MABORT    0x0010 /* 1=Send a STOP with no data 
-                                     * NB TBYTE must be clear       */
-#define IOP321_ICR_TBYTE     0x0008 /* 1=Send/Receive a byte. i2c clears */
-#define IOP321_ICR_NACK      0x0004 /* 1=reply with NACK */
-#define IOP321_ICR_MSTOP     0x0002 /* 1=send a STOP after next data byte */
-#define IOP321_ICR_MSTART    0x0001 /* 1=initiate a START */
-
+ */
+#define IOP321_ICR_SCLEN	0x0020	/* 1=SCL enable for master mode */
+#define IOP321_ICR_MABORT	0x0010	/* 1=Send a STOP with no data 
+					 * NB TBYTE must be clear */
+#define IOP321_ICR_TBYTE	0x0008	/* 1=Send/Receive a byte. i2c clears */
+#define IOP321_ICR_NACK		0x0004	/* 1=reply with NACK */
+#define IOP321_ICR_MSTOP	0x0002	/* 1=send a STOP after next data byte */
+#define IOP321_ICR_MSTART	0x0001	/* 1=initiate a START */
 
-#define IOP321_ISR_BERRD     0x0400 /* 1=BUS ERROR Detected */
-#define IOP321_ISR_SAD       0x0200 /* 1=Slave ADdress Detected */
-#define IOP321_ISR_GCAD      0x0100 /* 1=General Call Address Detected */
-#define IOP321_ISR_RXFULL    0x0080 /* 1=Receive Full */
-#define IOP321_ISR_TXEMPTY   0x0040 /* 1=Transmit Empty */
-#define IOP321_ISR_ALD       0x0020 /* 1=Arbitration Loss Detected */
-#define IOP321_ISR_SSD       0x0010 /* 1=Slave STOP Detected */
-#define IOP321_ISR_BBUSY     0x0008 /* 1=Bus BUSY */
-#define IOP321_ISR_UNITBUSY  0x0004 /* 1=Unit Busy */
-#define IOP321_ISR_NACK      0x0002 /* 1=Unit Rx or Tx a NACK */
-#define IOP321_ISR_RXREAD    0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */
 
-#define IOP321_ISR_CLEARBITS 0x07f0
+#define IOP321_ISR_BERRD	0x0400	/* 1=BUS ERROR Detected */
+#define IOP321_ISR_SAD		0x0200	/* 1=Slave ADdress Detected */
+#define IOP321_ISR_GCAD		0x0100	/* 1=General Call Address Detected */
+#define IOP321_ISR_RXFULL	0x0080	/* 1=Receive Full */
+#define IOP321_ISR_TXEMPTY	0x0040	/* 1=Transmit Empty */
+#define IOP321_ISR_ALD		0x0020	/* 1=Arbitration Loss Detected */
+#define IOP321_ISR_SSD		0x0010	/* 1=Slave STOP Detected */
+#define IOP321_ISR_BBUSY	0x0008	/* 1=Bus BUSY */
+#define IOP321_ISR_UNITBUSY	0x0004	/* 1=Unit Busy */
+#define IOP321_ISR_NACK		0x0002	/* 1=Unit Rx or Tx a NACK */
+#define IOP321_ISR_RXREAD	0x0001	/* 1=READ 0=WRITE (R/W bit of slave addr */
 
-#define IOP321_ISAR_SAMASK   0x007f 
+#define IOP321_ISR_CLEARBITS	0x07f0
 
-#define IOP321_IDBR_MASK     0x00ff
+#define IOP321_ISAR_SAMASK	0x007f
 
-#define IOP321_IBMR_SCL      0x0002
-#define IOP321_IBMR_SDA      0x0001
+#define IOP321_IDBR_MASK	0x00ff
 
-#define IOP321_GPOD_I2C0     0x00c0  /* clear these bits to enable ch0 */
-#define IOP321_GPOD_I2C1     0x0030  /* clear these bits to enable ch1 */
+#define IOP321_IBMR_SCL		0x0002
+#define IOP321_IBMR_SDA		0x0001
 
-#define MYSAR                0x02     /* SWAG a suitable slave address */
+#define IOP321_GPOD_I2C0	0x00c0	/* clear these bits to enable ch0 */
+#define IOP321_GPOD_I2C1	0x0030	/* clear these bits to enable ch1 */
 
-#define I2C_ERR              321
-#define I2C_ERR_BERR         (I2C_ERR+0)
-#define I2C_ERR_ALD          (I2C_ERR+1)
+#define MYSAR			0x02	/* SWAG a suitable slave address */
 
+#define I2C_ERR			321
+#define I2C_ERR_BERR		(I2C_ERR+0)
+#define I2C_ERR_ALD		(I2C_ERR+1)
 
-typedef volatile u32* r32;
 
 struct iop3xx_biu {                /* Bus Interface Unit - the hardware */
 /* physical hardware defs - regs*/
-	r32 CR;
-	r32 SR;
-	r32 SAR;
-	r32 DBR;
-	r32 BMR;
+	u32 *CR;
+	u32 *SR;
+	u32 *SAR;
+	u32 *DBR;
+	u32 *BMR;
 /* irq bit vector */
 	u32 irq;
 /* stored flags */
@@ -111,10 +109,10 @@ struct i2c_algo_iop3xx_data {
 	struct iop3xx_biu* biu;
 };
 
-#define REGION_START( adap )  ((u32)((adap)->biu->CR))
-#define REGION_END( adap )    ((u32)((adap)->biu->BMR+1))
-#define REGION_LENGTH( adap ) (REGION_END(adap)-REGION_START(adap))
+#define REGION_START(adap)	((u32)((adap)->biu->CR))
+#define REGION_END(adap)	((u32)((adap)->biu->BMR+1))
+#define REGION_LENGTH(adap)	(REGION_END(adap)-REGION_START(adap))
 
-#define IRQ_STATUS_MASK( adap ) (1<<adap->biu->irq)
+#define IRQ_STATUS_MASK(adap)	(1<<adap->biu->irq)
 
 #endif /* I2C_IOP3XX_H */