[AGPGART] don't dereference agp_bridge in generic-3.0.c

Yet more from Christoph..
>If agp_3_0_node_enable gets a struct agp_bridge_data * all of the
>generic-3.0.c can be cleaned up easily to never look at agp_bridge
>directly.  Now only backend.c, generic.c and the actual drivers
>are left looking at it:)

drivers/char/agp/agp.h

@@ -384,7 +384,7 @@ void agp_free_key(int key);
 int agp_num_entries(void);
 u32 agp_collect_device_status(u32 mode, u32 command);
 void agp_device_command(u32 command, int agp_v3);
-int agp_3_0_node_enable(u32 mode, u32 minor);
+int agp_3_0_node_enable(struct agp_bridge_data *bridge, u32 mode, u32 minor);
 void global_cache_flush(void);
 
 /* Standard agp registers */

drivers/char/agp/generic-3.0.c

@@ -59,7 +59,8 @@ static void agp_3_0_dev_list_sort(struct agp_3_0_dev *list, unsigned int ndevs)
  * lying behind it...)
  */
 
-static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigned int ndevs)
+static int agp_3_0_isochronous_node_enable(struct agp_bridge_data *bridge,
+		struct agp_3_0_dev *dev_list, unsigned int ndevs)
 {
 	/*
 	 * Convenience structure to make the calculations clearer
@@ -74,7 +75,7 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
 		struct agp_3_0_dev *dev;
 	};
 
-	struct pci_dev *td = agp_bridge->dev, *dev;
+	struct pci_dev *td = bridge->dev, *dev;
 	struct list_head *head = &dev_list->list, *pos;
 	struct agp_3_0_dev *cur;
 	struct isoch_data *master, target;
@@ -113,8 +114,8 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
 	 */
 	agp_3_0_dev_list_sort(dev_list, ndevs);
 
-	pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
-	pci_read_config_dword(td, agp_bridge->capndx+AGPSTAT, &tstatus);
+	pci_read_config_dword(td, bridge->capndx + 0x0c, &tnistat);
+	pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus);
 
 	/* Extract power-on defaults from the target */
 	target.maxbw = (tnistat >> 16) & 0xff;
@@ -166,13 +167,13 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
 	 * in the target's NISTAT register, so we need to do this now
 	 * to get an accurate value for ISOCH_N later.
 	 */
-	pci_read_config_word(td, agp_bridge->capndx + 0x20, &tnicmd);
+	pci_read_config_word(td, bridge->capndx + 0x20, &tnicmd);
 	tnicmd &= ~(0x3 << 6);
 	tnicmd |= target.y << 6;
-	pci_write_config_word(td, agp_bridge->capndx + 0x20, tnicmd);
+	pci_write_config_word(td, bridge->capndx + 0x20, tnicmd);
 
 	/* Reread the target's ISOCH_N */
-	pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
+	pci_read_config_dword(td, bridge->capndx + 0x0c, &tnistat);
 	target.n = (tnistat >> 8) & 0xff;
 
 	/* Calculate the minimum ISOCH_N needed by each master */
@@ -284,7 +285,8 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
  * target by ndevs.  Distribute this many slots to each AGP 3.0 device,
  * giving any left over slots to the last device in dev_list.
  */
-static void agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsigned int ndevs)
+static void agp_3_0_nonisochronous_node_enable(struct agp_bridge_data *bridge,
+		struct agp_3_0_dev *dev_list, unsigned int ndevs)
 {
 	struct agp_3_0_dev *cur;
 	struct list_head *head = &dev_list->list, *pos;
@@ -292,7 +294,7 @@ static void agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, uns
 	u32 trq, mrq, rem;
 	unsigned int cdev = 0;
 
-	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x04, &tstatus);
+	pci_read_config_dword(bridge->dev, bridge->capndx + 0x04, &tstatus);
 
 	trq = (tstatus >> 24) & 0xff;
 	mrq = trq / ndevs;
@@ -313,9 +315,9 @@ static void agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, uns
  * Fully configure and enable an AGP 3.0 host bridge and all the devices
  * lying behind it.
  */
-int agp_3_0_node_enable(u32 mode, u32 minor)
+int agp_3_0_node_enable(struct agp_bridge_data *bridge, u32 mode, u32 minor)
 {
-	struct pci_dev *td = agp_bridge->dev, *dev;
+	struct pci_dev *td = bridge->dev, *dev;
 	u8 mcapndx;
 	u32 isoch, arqsz, cal_cycle, tmp, rate;
 	u32 tstatus, tcmd, mcmd, mstatus, ncapid;
@@ -375,7 +377,7 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
 	}
 
 	/* Extract some power-on defaults from the target */
-	pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
+	pci_read_config_dword(td, bridge->capndx + 0x04, &tstatus);
 	isoch     = (tstatus >> 17) & 0x1;
 	arqsz     = (tstatus >> 13) & 0x7;
 	cal_cycle = (tstatus >> 10) & 0x7;
@@ -467,15 +469,15 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
 	 * masters.  This process is dramatically different depending on
 	 * whether isochronous transfers are supported.
 	 */
-	if(isoch != 0) {
-		if((ret = agp_3_0_isochronous_node_enable(dev_list, ndevs)) != 0) {
-			printk (KERN_INFO PFX "Something bad happened setting up isochronous xfers. "
-				"Falling back to non-isochronous xfer mode.\n");
-			agp_3_0_nonisochronous_node_enable(dev_list,ndevs);
+	if (isoch) {
+		ret = agp_3_0_isochronous_node_enable(bridge, dev_list, ndevs);
+		if (ret) {
+			printk(KERN_INFO PFX "Something bad happened setting "
+			       "up isochronous xfers.  Falling back to "
+			       "non-isochronous xfer mode.\n");
 		}
-	} else {
-		agp_3_0_nonisochronous_node_enable(dev_list,ndevs);
 	}
+	agp_3_0_nonisochronous_node_enable(bridge, dev_list, ndevs);
 
 	/*
 	 * Set the calculated minimum supported cal_cycle and minimum
@@ -483,7 +485,7 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
 	 * Also set the AGP_ENABLE bit, effectively 'turning on' the
 	 * target (this has to be done _before_ turning on the masters).
 	 */
-	pci_read_config_dword(td, agp_bridge->capndx+AGPCMD, &tcmd);
+	pci_read_config_dword(td, bridge->capndx+AGPCMD, &tcmd);
 
 	tcmd &= ~(0x7 << 10);
 	tcmd &= ~0x7;
@@ -492,7 +494,7 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
 	tcmd |= 0x1 << 8;
 	tcmd |= rate;
 
-	pci_write_config_dword(td, agp_bridge->capndx+AGPCMD, tcmd);
+	pci_write_config_dword(td, bridge->capndx+AGPCMD, tcmd);
 
 	/*
 	 * Set the target's advertised arqsz value, the minimum supported

drivers/char/agp/generic.c

@@ -461,7 +461,7 @@ void agp_generic_enable(u32 mode)
 		pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0);
 		/* Check to see if we are operating in 3.0 mode */
 		if((agp_3_0 >> 3) & 0x1) {
-			agp_3_0_node_enable(mode, minor);
+			agp_3_0_node_enable(agp_bridge, mode, minor);
 			return;
 		} else {
 			printk (KERN_INFO PFX "not in AGP 3.0 mode, falling back to 2.x\n");