Commit eadc0ef1 authored by Adrian Hunter's avatar Adrian Hunter Committed by Greg Kroah-Hartman

perf intel-pt: Fix MTC timing after overflow

commit dd27b87a upstream.

On some platforms, overflows will clear before MTC wraparound, and there
is no following TSC/TMA packet. In that case the previous TMA is valid.
Since there will be a valid TMA either way, stop setting 'have_tma' to
false upon overflow.
Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1527762225-26024-4-git-send-email-adrian.hunter@intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a6338a81
...@@ -1268,7 +1268,6 @@ static int intel_pt_overflow(struct intel_pt_decoder *decoder) ...@@ -1268,7 +1268,6 @@ static int intel_pt_overflow(struct intel_pt_decoder *decoder)
{ {
intel_pt_log("ERROR: Buffer overflow\n"); intel_pt_log("ERROR: Buffer overflow\n");
intel_pt_clear_tx_flags(decoder); intel_pt_clear_tx_flags(decoder);
decoder->have_tma = false;
decoder->cbr = 0; decoder->cbr = 0;
decoder->timestamp_insn_cnt = 0; decoder->timestamp_insn_cnt = 0;
decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC; decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC;
......
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