Commit eba8ba8a authored by Chunyan Zhang's avatar Chunyan Zhang Committed by Stephen Boyd

dt-bindings: clk: sprd: add bindings for sc9863a clock controller

add a new bindings to describe sc9863a clock compatible string.
Signed-off-by: default avatarChunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-4-zhang.lyra@gmail.comReviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 2112d1dd
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: SC9863A Clock Control Unit Device Tree Bindings
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
properties:
"#clock-cells":
const: 1
compatible :
enum:
- sprd,sc9863a-ap-clk
- sprd,sc9863a-aon-clk
- sprd,sc9863a-apahb-gate
- sprd,sc9863a-pmu-gate
- sprd,sc9863a-aonapb-gate
- sprd,sc9863a-pll
- sprd,sc9863a-mpll
- sprd,sc9863a-rpll
- sprd,sc9863a-dpll
- sprd,sc9863a-mm-gate
- sprd,sc9863a-apapb-gate
clocks:
minItems: 1
maxItems: 4
description: |
The input parent clock(s) phandle for this clock, only list fixed
clocks which are declared in devicetree.
clock-names:
minItems: 1
maxItems: 4
items:
- const: ext-26m
- const: ext-32k
- const: ext-4m
- const: rco-100m
reg:
maxItems: 1
required:
- compatible
- '#clock-cells'
if:
properties:
compatible:
enum:
- sprd,sc9863a-ap-clk
- sprd,sc9863a-aon-clk
then:
required:
- reg
else:
description: |
Other SC9863a clock nodes should be the child of a syscon node in
which compatible string shoule be:
"sprd,sc9863a-glbregs", "syscon", "simple-mfd"
The 'reg' property for the clock node is also required if there is a sub
range of registers for the clocks.
examples:
- |
ap_clk: clock-controller@21500000 {
compatible = "sprd,sc9863a-ap-clk";
reg = <0 0x21500000 0 0x1000>;
clocks = <&ext_26m>, <&ext_32k>;
clock-names = "ext-26m", "ext-32k";
#clock-cells = <1>;
};
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
ap_ahb_regs: syscon@20e00000 {
compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
reg = <0 0x20e00000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x20e00000 0x4000>;
apahb_gate: apahb-gate@0 {
compatible = "sprd,sc9863a-apahb-gate";
reg = <0x0 0x1020>;
#clock-cells = <1>;
};
};
};
...
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