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Commit ebe02de2 authored by Himanshu Jha's avatar Himanshu Jha Committed by Alex Deucher
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drm/amd/powerplay/hwmgr: Remove null check before kfree 

kfree on NULL pointer is a no-op and therefore checking is redundant.
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarHimanshu Jha <himanshujha199640@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c5927537
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Showing with 53 additions and 105 deletions
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
View file @ ebe02de2
...@@ -1225,10 +1225,8 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) ...@@ -1225,10 +1225,8 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
}
kfree(hwmgr->backend); kfree(hwmgr->backend);
hwmgr->backend = NULL; hwmgr->backend = NULL;
......
drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
View file @ ebe02de2
...@@ -1652,85 +1652,53 @@ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) ...@@ -1652,85 +1652,53 @@ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
if (hwmgr->chip_id == CHIP_RAVEN) if (hwmgr->chip_id == CHIP_RAVEN)
return 0; return 0;
if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) { kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
}
if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) { kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
}
if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) { kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
}
if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
}
if (NULL != hwmgr->dyn_state.valid_mclk_values) { kfree(hwmgr->dyn_state.valid_mclk_values);
kfree(hwmgr->dyn_state.valid_mclk_values); hwmgr->dyn_state.valid_mclk_values = NULL;
hwmgr->dyn_state.valid_mclk_values = NULL;
}
if (NULL != hwmgr->dyn_state.valid_sclk_values) { kfree(hwmgr->dyn_state.valid_sclk_values);
kfree(hwmgr->dyn_state.valid_sclk_values); hwmgr->dyn_state.valid_sclk_values = NULL;
hwmgr->dyn_state.valid_sclk_values = NULL;
}
if (NULL != hwmgr->dyn_state.cac_leakage_table) { kfree(hwmgr->dyn_state.cac_leakage_table);
kfree(hwmgr->dyn_state.cac_leakage_table); hwmgr->dyn_state.cac_leakage_table = NULL;
hwmgr->dyn_state.cac_leakage_table = NULL;
}
if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) { kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
}
if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) { kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
}
if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) { kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
}
if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) { kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
}
if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) { kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
}
if (NULL != hwmgr->dyn_state.cac_dtp_table) { kfree(hwmgr->dyn_state.cac_dtp_table);
kfree(hwmgr->dyn_state.cac_dtp_table); hwmgr->dyn_state.cac_dtp_table = NULL;
hwmgr->dyn_state.cac_dtp_table = NULL;
}
if (NULL != hwmgr->dyn_state.ppm_parameter_table) { kfree(hwmgr->dyn_state.ppm_parameter_table);
kfree(hwmgr->dyn_state.ppm_parameter_table); hwmgr->dyn_state.ppm_parameter_table = NULL;
hwmgr->dyn_state.ppm_parameter_table = NULL;
}
if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) { kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
}
if (NULL != hwmgr->dyn_state.vq_budgeting_table) { kfree(hwmgr->dyn_state.vq_budgeting_table);
kfree(hwmgr->dyn_state.vq_budgeting_table); hwmgr->dyn_state.vq_budgeting_table = NULL;
hwmgr->dyn_state.vq_budgeting_table = NULL;
}
return 0; return 0;
} }
......
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
View file @ ebe02de2
...@@ -552,35 +552,21 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) ...@@ -552,35 +552,21 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
phm_destroy_table(hwmgr, &(hwmgr->power_down_asic)); phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
phm_destroy_table(hwmgr, &(hwmgr->setup_asic)); phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
if (pinfo->vdd_dep_on_dcefclk) { kfree(pinfo->vdd_dep_on_dcefclk);
kfree(pinfo->vdd_dep_on_dcefclk); pinfo->vdd_dep_on_dcefclk = NULL;
pinfo->vdd_dep_on_dcefclk = NULL; kfree(pinfo->vdd_dep_on_socclk);
} pinfo->vdd_dep_on_socclk = NULL;
if (pinfo->vdd_dep_on_socclk) { kfree(pinfo->vdd_dep_on_fclk);
kfree(pinfo->vdd_dep_on_socclk); pinfo->vdd_dep_on_fclk = NULL;
pinfo->vdd_dep_on_socclk = NULL; kfree(pinfo->vdd_dep_on_dispclk);
} pinfo->vdd_dep_on_dispclk = NULL;
if (pinfo->vdd_dep_on_fclk) { kfree(pinfo->vdd_dep_on_dppclk);
kfree(pinfo->vdd_dep_on_fclk); pinfo->vdd_dep_on_dppclk = NULL;
pinfo->vdd_dep_on_fclk = NULL; kfree(pinfo->vdd_dep_on_phyclk);
} pinfo->vdd_dep_on_phyclk = NULL;
if (pinfo->vdd_dep_on_dispclk) {
kfree(pinfo->vdd_dep_on_dispclk); kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
pinfo->vdd_dep_on_dispclk = NULL; hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
}
if (pinfo->vdd_dep_on_dppclk) {
kfree(pinfo->vdd_dep_on_dppclk);
pinfo->vdd_dep_on_dppclk = NULL;
}
if (pinfo->vdd_dep_on_phyclk) {
kfree(pinfo->vdd_dep_on_phyclk);
pinfo->vdd_dep_on_phyclk = NULL;
}
if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
}
kfree(hwmgr->backend); kfree(hwmgr->backend);
hwmgr->backend = NULL; hwmgr->backend = NULL;
......
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View file @ ebe02de2
...@@ -2282,15 +2282,11 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) ...@@ -2282,15 +2282,11 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{ {
if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) { kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
}
pp_smu7_thermal_fini(hwmgr); pp_smu7_thermal_fini(hwmgr);
if (NULL != hwmgr->backend) { kfree(hwmgr->backend);
kfree(hwmgr->backend); hwmgr->backend = NULL;
hwmgr->backend = NULL;
}
return 0; return 0;
} }
......
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