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Commit ecabdc6a authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Refresh skylakex metrics and events 

Update the skylakex metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. uncore-other.json
changes due to events now being sorted. The formatting changes
increase consistency across the json files.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-19-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 00ca782e
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Showing with 18426 additions and 16497 deletions
tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
View file @ ecabdc6a
[ [
{ {
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -11,8 +9,6 @@ ...@@ -11,8 +9,6 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -21,8 +17,6 @@ ...@@ -21,8 +17,6 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -31,8 +25,6 @@ ...@@ -31,8 +25,6 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -41,8 +33,6 @@ ...@@ -41,8 +33,6 @@
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -51,8 +41,6 @@ ...@@ -51,8 +41,6 @@
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -61,8 +49,6 @@ ...@@ -61,8 +49,6 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -71,8 +57,6 @@ ...@@ -71,8 +57,6 @@
}, },
{ {
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
...@@ -81,8 +65,6 @@ ...@@ -81,8 +65,6 @@
}, },
{ {
"BriefDescription": "Cycles with any input/output SSE or FP assist", "BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY", "EventName": "FP_ASSIST.ANY",
......
tools/perf/pmu-events/arch/x86/skylakex/other.json
View file @ ecabdc6a
[ [
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
...@@ -11,8 +9,6 @@ ...@@ -11,8 +9,6 @@
}, },
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
...@@ -21,8 +17,6 @@ ...@@ -21,8 +17,6 @@
}, },
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
...@@ -31,8 +25,6 @@ ...@@ -31,8 +25,6 @@
}, },
{ {
"BriefDescription": "Core cycles the core was throttled due to a pending power level request.", "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28", "EventCode": "0x28",
"EventName": "CORE_POWER.THROTTLE", "EventName": "CORE_POWER.THROTTLE",
"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
...@@ -41,8 +33,6 @@ ...@@ -41,8 +33,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -50,8 +40,6 @@ ...@@ -50,8 +40,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -59,8 +47,6 @@ ...@@ -59,8 +47,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -68,8 +54,6 @@ ...@@ -68,8 +54,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -77,8 +61,6 @@ ...@@ -77,8 +61,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -86,8 +68,6 @@ ...@@ -86,8 +68,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -95,8 +75,6 @@ ...@@ -95,8 +75,6 @@
}, },
{ {
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF", "EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
...@@ -104,8 +82,6 @@ ...@@ -104,8 +82,6 @@
}, },
{ {
"BriefDescription": "Number of hardware interrupts received by the processor.", "BriefDescription": "Number of hardware interrupts received by the processor.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCB", "EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED", "EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts the number of hardware interruptions received by the processor.", "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
...@@ -114,8 +90,6 @@ ...@@ -114,8 +90,6 @@
}, },
{ {
"BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE", "EventCode": "0xFE",
"EventName": "IDI_MISC.WB_DOWNGRADE", "EventName": "IDI_MISC.WB_DOWNGRADE",
"PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
...@@ -124,8 +98,6 @@ ...@@ -124,8 +98,6 @@
}, },
{ {
"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE", "EventCode": "0xFE",
"EventName": "IDI_MISC.WB_UPGRADE", "EventName": "IDI_MISC.WB_UPGRADE",
"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
...@@ -134,8 +106,6 @@ ...@@ -134,8 +106,6 @@
}, },
{ {
"BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x09", "EventCode": "0x09",
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
......
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