Commit ed2759f5 authored by Sinan Kaya's avatar Sinan Kaya Committed by Kleber Sacilotto de Souza

net: ena: Eliminate duplicate barriers on weakly-ordered archs

BugLink: http://bugs.launchpad.net/bugs/1792044

Code includes barrier() followed by writel(). writel() already has a
barrier on some architectures like arm64.

This ends up CPU observing two barriers back to back before executing the
register write.

Create a new wrapper function with relaxed write operator. Use the new
wrapper when a write is following a barrier().

Since code already has an explicit barrier call, changing writel() to
writel_relaxed() and adding mmiowb() for ordering protection.
Signed-off-by: default avatarSinan Kaya <okaya@codeaurora.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
(cherry picked from commit 6d2e1a8d)
Signed-off-by: default avatarKamal Mostafa <kamal@canonical.com>
Acked-by: default avatarAcked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: default avatarBrad Figg <brad.figg@canonical.com>
Signed-off-by: default avatarKamal Mostafa <kamal@canonical.com>
parent 40c8b895
...@@ -631,8 +631,10 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) ...@@ -631,8 +631,10 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
*/ */
wmb(); wmb();
writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); writel_relaxed(mmio_read_reg,
ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
mmiowb();
for (i = 0; i < timeout; i++) { for (i = 0; i < timeout; i++) {
if (read_resp->req_id == mmio_read->seq_num) if (read_resp->req_id == mmio_read->seq_num)
break; break;
...@@ -1826,7 +1828,9 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) ...@@ -1826,7 +1828,9 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
/* write the aenq doorbell after all AENQ descriptors were read */ /* write the aenq doorbell after all AENQ descriptors were read */
mb(); mb();
writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); writel_relaxed((u32)aenq->head,
dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
mmiowb();
} }
int ena_com_dev_reset(struct ena_com_dev *ena_dev, int ena_com_dev_reset(struct ena_com_dev *ena_dev,
......
...@@ -107,7 +107,8 @@ static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq) ...@@ -107,7 +107,8 @@ static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)
return io_sq->q_depth - 1 - cnt; return io_sq->q_depth - 1 - cnt;
} }
static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq) static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq,
bool relaxed)
{ {
u16 tail; u16 tail;
...@@ -116,7 +117,10 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq) ...@@ -116,7 +117,10 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
pr_debug("write submission queue doorbell for queue: %d tail: %d\n", pr_debug("write submission queue doorbell for queue: %d tail: %d\n",
io_sq->qid, tail); io_sq->qid, tail);
writel(tail, io_sq->db_addr); if (relaxed)
writel_relaxed(tail, io_sq->db_addr);
else
writel(tail, io_sq->db_addr);
return 0; return 0;
} }
......
...@@ -563,7 +563,8 @@ static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num) ...@@ -563,7 +563,8 @@ static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
* issue a doorbell * issue a doorbell
*/ */
wmb(); wmb();
ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq, true);
mmiowb();
} }
rx_ring->next_to_use = next_to_use; rx_ring->next_to_use = next_to_use;
...@@ -2137,7 +2138,7 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -2137,7 +2138,7 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (netif_xmit_stopped(txq) || !skb->xmit_more) { if (netif_xmit_stopped(txq) || !skb->xmit_more) {
/* trigger the dma engine */ /* trigger the dma engine */
ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq, false);
u64_stats_update_begin(&tx_ring->syncp); u64_stats_update_begin(&tx_ring->syncp);
tx_ring->tx_stats.doorbells++; tx_ring->tx_stats.doorbells++;
u64_stats_update_end(&tx_ring->syncp); u64_stats_update_end(&tx_ring->syncp);
......
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