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Commit ed3d95fe authored by Damian Muszynski's avatar Damian Muszynski Committed by Herbert Xu
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crypto: qat - make ring to service map common for QAT GEN4 

The function get_ring_to_svc_map() is present in both 420xx and
4xxx drivers. Rework the logic to make it generic to GEN4 devices
and move it to qat_common/adf_gen4_hw_data.c.
Signed-off-by: default avatarDamian Muszynski <damian.muszynski@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent a20a6060
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Showing with 90 additions and 112 deletions
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
View file @ ed3d95fe
......@@ -361,61 +361,6 @@ static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
}
}
static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
{
enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { };
const struct adf_fw_config *fw_config;
u16 ring_to_svc_map;
int i, j;
fw_config = get_fw_config(accel_dev);
if (!fw_config)
return 0;
/* If dcc, all rings handle compression requests */
if (adf_get_service_enabled(accel_dev) == SVC_DCC) {
for (i = 0; i < RP_GROUP_COUNT; i++)
rps[i] = COMP;
goto set_mask;
}
for (i = 0; i < RP_GROUP_COUNT; i++) {
switch (fw_config[i].ae_mask) {
case ADF_AE_GROUP_0:
j = RP_GROUP_0;
break;
case ADF_AE_GROUP_1:
j = RP_GROUP_1;
break;
default:
return 0;
}
switch (fw_config[i].obj) {
case ADF_FW_SYM_OBJ:
rps[j] = SYM;
break;
case ADF_FW_ASYM_OBJ:
rps[j] = ASYM;
break;
case ADF_FW_DC_OBJ:
rps[j] = COMP;
break;
default:
rps[j] = 0;
break;
}
}
set_mask:
ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |
rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;
return ring_to_svc_map;
}
static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,
const char * const fw_objs[], int num_objs)
{
......@@ -441,6 +386,20 @@ static const char *uof_get_name_420xx(struct adf_accel_dev *accel_dev, u32 obj_n
return uof_get_name(accel_dev, obj_num, adf_420xx_fw_objs, num_fw_objs);
}
static int uof_get_obj_type(struct adf_accel_dev *accel_dev, u32 obj_num)
{
const struct adf_fw_config *fw_config;
if (obj_num >= uof_get_num_objs(accel_dev))
return -EINVAL;
fw_config = get_fw_config(accel_dev);
if (!fw_config)
return -EINVAL;
return fw_config[obj_num].obj;
}
static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
{
const struct adf_fw_config *fw_config;
......@@ -504,12 +463,13 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
hw_data->fw_mmp_name = ADF_420XX_MMP;
hw_data->uof_get_name = uof_get_name_420xx;
hw_data->uof_get_num_objs = uof_get_num_objs;
hw_data->uof_get_obj_type = uof_get_obj_type;
hw_data->uof_get_ae_mask = uof_get_ae_mask;
hw_data->get_rp_group = get_rp_group;
hw_data->get_ena_thd_mask = get_ena_thd_mask;
hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
hw_data->get_ring_to_svc_map = get_ring_to_svc_map;
hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;
hw_data->disable_iov = adf_disable_sriov;
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
hw_data->enable_pm = adf_gen4_enable_pm;
......
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
View file @ ed3d95fe
......@@ -320,61 +320,6 @@ static u32 get_ena_thd_mask_401xx(struct adf_accel_dev *accel_dev, u32 obj_num)
}
}
static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
{
enum adf_cfg_service_type rps[RP_GROUP_COUNT];
const struct adf_fw_config *fw_config;
u16 ring_to_svc_map;
int i, j;
fw_config = get_fw_config(accel_dev);
if (!fw_config)
return 0;
/* If dcc, all rings handle compression requests */
if (adf_get_service_enabled(accel_dev) == SVC_DCC) {
for (i = 0; i < RP_GROUP_COUNT; i++)
rps[i] = COMP;
goto set_mask;
}
for (i = 0; i < RP_GROUP_COUNT; i++) {
switch (fw_config[i].ae_mask) {
case ADF_AE_GROUP_0:
j = RP_GROUP_0;
break;
case ADF_AE_GROUP_1:
j = RP_GROUP_1;
break;
default:
return 0;
}
switch (fw_config[i].obj) {
case ADF_FW_SYM_OBJ:
rps[j] = SYM;
break;
case ADF_FW_ASYM_OBJ:
rps[j] = ASYM;
break;
case ADF_FW_DC_OBJ:
rps[j] = COMP;
break;
default:
rps[j] = 0;
break;
}
}
set_mask:
ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |
rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;
return ring_to_svc_map;
}
static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,
const char * const fw_objs[], int num_objs)
{
......@@ -407,6 +352,20 @@ static const char *uof_get_name_402xx(struct adf_accel_dev *accel_dev, u32 obj_n
return uof_get_name(accel_dev, obj_num, adf_402xx_fw_objs, num_fw_objs);
}
static int uof_get_obj_type(struct adf_accel_dev *accel_dev, u32 obj_num)
{
const struct adf_fw_config *fw_config;
if (obj_num >= uof_get_num_objs(accel_dev))
return -EINVAL;
fw_config = get_fw_config(accel_dev);
if (!fw_config)
return -EINVAL;
return fw_config[obj_num].obj;
}
static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
{
const struct adf_fw_config *fw_config;
......@@ -487,11 +446,12 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
break;
}
hw_data->uof_get_num_objs = uof_get_num_objs;
hw_data->uof_get_obj_type = uof_get_obj_type;
hw_data->uof_get_ae_mask = uof_get_ae_mask;
hw_data->get_rp_group = get_rp_group;
hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
hw_data->get_ring_to_svc_map = get_ring_to_svc_map;
hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;
hw_data->disable_iov = adf_disable_sriov;
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
hw_data->enable_pm = adf_gen4_enable_pm;
......
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
View file @ ed3d95fe
......@@ -248,6 +248,7 @@ struct adf_hw_device_data {
void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
u32 (*uof_get_num_objs)(struct adf_accel_dev *accel_dev);
int (*uof_get_obj_type)(struct adf_accel_dev *accel_dev, u32 obj_num);
u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
int (*get_rp_group)(struct adf_accel_dev *accel_dev, u32 ae_mask);
u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
......
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
View file @ ed3d95fe
......@@ -4,6 +4,7 @@
#include "adf_accel_devices.h"
#include "adf_cfg_services.h"
#include "adf_common_drv.h"
#include "adf_fw_config.h"
#include "adf_gen4_hw_data.h"
#include "adf_gen4_pm.h"
......@@ -433,3 +434,58 @@ int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev)
return 0;
}
EXPORT_SYMBOL_GPL(adf_gen4_init_thd2arb_map);
u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev)
{
struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { };
unsigned int ae_mask, start_id, worker_obj_cnt, i;
u16 ring_to_svc_map;
int rp_group;
if (!hw_data->get_rp_group || !hw_data->uof_get_ae_mask ||
!hw_data->uof_get_obj_type || !hw_data->uof_get_num_objs)
return 0;
/* If dcc, all rings handle compression requests */
if (adf_get_service_enabled(accel_dev) == SVC_DCC) {
for (i = 0; i < RP_GROUP_COUNT; i++)
rps[i] = COMP;
goto set_mask;
}
worker_obj_cnt = hw_data->uof_get_num_objs(accel_dev) -
ADF_GEN4_ADMIN_ACCELENGINES;
start_id = worker_obj_cnt - RP_GROUP_COUNT;
for (i = start_id; i < worker_obj_cnt; i++) {
ae_mask = hw_data->uof_get_ae_mask(accel_dev, i);
rp_group = hw_data->get_rp_group(accel_dev, ae_mask);
if (rp_group >= RP_GROUP_COUNT || rp_group < RP_GROUP_0)
return 0;
switch (hw_data->uof_get_obj_type(accel_dev, i)) {
case ADF_FW_SYM_OBJ:
rps[rp_group] = SYM;
break;
case ADF_FW_ASYM_OBJ:
rps[rp_group] = ASYM;
break;
case ADF_FW_DC_OBJ:
rps[rp_group] = COMP;
break;
default:
rps[rp_group] = 0;
break;
}
}
set_mask:
ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT |
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT |
rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT |
rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT;
return ring_to_svc_map;
}
EXPORT_SYMBOL_GPL(adf_gen4_get_ring_to_svc_map);
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
View file @ ed3d95fe
......@@ -235,5 +235,6 @@ int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);
void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev);
void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev);
u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev);
#endif
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