Commit ee3eaee6 authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King

ARM: 8704/1: semihosting: use proper instruction on v7m processors

The svc instruction doesn't exist on v7m processors. Semihosting ops are
invoked with the bkpt instruction instead.
Signed-off-by: default avatarNicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 6042b8c7
...@@ -23,7 +23,11 @@ ENTRY(putc) ...@@ -23,7 +23,11 @@ ENTRY(putc)
strb r0, [r1] strb r0, [r1]
mov r0, #0x03 @ SYS_WRITEC mov r0, #0x03 @ SYS_WRITEC
ARM( svc #0x123456 ) ARM( svc #0x123456 )
#ifdef CONFIG_CPU_V7M
THUMB( bkpt #0xab )
#else
THUMB( svc #0xab ) THUMB( svc #0xab )
#endif
mov pc, lr mov pc, lr
.align 2 .align 2
1: .word _GLOBAL_OFFSET_TABLE_ - . 1: .word _GLOBAL_OFFSET_TABLE_ - .
......
...@@ -115,7 +115,11 @@ ENTRY(printascii) ...@@ -115,7 +115,11 @@ ENTRY(printascii)
mov r1, r0 mov r1, r0
mov r0, #0x04 @ SYS_WRITE0 mov r0, #0x04 @ SYS_WRITE0
ARM( svc #0x123456 ) ARM( svc #0x123456 )
#ifdef CONFIG_CPU_V7M
THUMB( bkpt #0xab )
#else
THUMB( svc #0xab ) THUMB( svc #0xab )
#endif
ret lr ret lr
ENDPROC(printascii) ENDPROC(printascii)
...@@ -124,7 +128,11 @@ ENTRY(printch) ...@@ -124,7 +128,11 @@ ENTRY(printch)
strb r0, [r1] strb r0, [r1]
mov r0, #0x03 @ SYS_WRITEC mov r0, #0x03 @ SYS_WRITEC
ARM( svc #0x123456 ) ARM( svc #0x123456 )
#ifdef CONFIG_CPU_V7M
THUMB( bkpt #0xab )
#else
THUMB( svc #0xab ) THUMB( svc #0xab )
#endif
ret lr ret lr
ENDPROC(printch) ENDPROC(printch)
......
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