staging: olpc_dcon: add OLPC display controller (DCON) support

This adds DCON support for the OLPC XO.  The DCON is found in XO-1 and
XO-1.5 hardware.  The XO-1 has a CS5536 southbridge, while the XO-1.5
has a Via chipset; the GPIO magic that's necessary to communicate with
the DCON chip is unfortunately different across both platforms.  This
driver supports both.

This driver is in bad state atm, so I'm requesting its inclusion into
staging so it can be cleaned up while staying in the kernel tree.

Original driver by Dave Woodhouse, and modified extensively by
Jordan Crouse, myself, Deepak Saxena, Paul Fox, Daniel Drake, and
probably others that I've missed.
Signed-off-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

drivers/staging/Kconfig

@@ -69,6 +69,8 @@ source "drivers/staging/rt2870/Kconfig"
 
 source "drivers/staging/comedi/Kconfig"
 
+source "drivers/staging/olpc_dcon/Kconfig"
+
 source "drivers/staging/asus_oled/Kconfig"
 
 source "drivers/staging/panel/Kconfig"

drivers/staging/Makefile

@@ -18,6 +18,7 @@ obj-$(CONFIG_BRCM80211)		+= brcm80211/
 obj-$(CONFIG_RT2860)		+= rt2860/
 obj-$(CONFIG_RT2870)		+= rt2870/
 obj-$(CONFIG_COMEDI)		+= comedi/
+obj-$(CONFIG_FB_OLPC_DCON)	+= olpc_dcon/
 obj-$(CONFIG_ASUS_OLED)		+= asus_oled/
 obj-$(CONFIG_PANEL)		+= panel/
 obj-$(CONFIG_R8187SE)		+= rtl8187se/

drivers/staging/olpc_dcon/Kconfig

+config FB_OLPC_DCON
+	tristate "One Laptop Per Child Display CONtroller support"
+	depends on OLPC
+	select I2C
+	---help---
+	  Add support for the OLPC XO DCON controller.  This controller is
+	  only available on OLPC platforms.   Unless you have one of these
+	  platforms, you will want to say 'N'.

drivers/staging/olpc_dcon/Makefile

+obj-$(CONFIG_FB_OLPC_DCON)	+= olpc_dcon.o

drivers/staging/olpc_dcon/olpc_dcon.h

+#ifndef OLPC_DCON_H_
+#define OLPC_DCON_H_
+
+/* DCON registers */
+
+#define DCON_REG_ID		 0
+#define DCON_REG_MODE		 1
+
+#define MODE_PASSTHRU	(1<<0)
+#define MODE_SLEEP	(1<<1)
+#define MODE_SLEEP_AUTO	(1<<2)
+#define MODE_BL_ENABLE	(1<<3)
+#define MODE_BLANK	(1<<4)
+#define MODE_CSWIZZLE	(1<<5)
+#define MODE_COL_AA	(1<<6)
+#define MODE_MONO_LUMA	(1<<7)
+#define MODE_SCAN_INT	(1<<8)
+#define MODE_CLOCKDIV	(1<<9)
+#define MODE_DEBUG	(1<<14)
+#define MODE_SELFTEST	(1<<15)
+
+#define DCON_REG_HRES		2
+#define DCON_REG_HTOTAL		3
+#define DCON_REG_HSYNC_WIDTH	4
+#define DCON_REG_VRES		5
+#define DCON_REG_VTOTAL		6
+#define DCON_REG_VSYNC_WIDTH	7
+#define DCON_REG_TIMEOUT	8
+#define DCON_REG_SCAN_INT	9
+#define DCON_REG_BRIGHT		10
+
+/* GPIO registers (CS5536) */
+
+#define MSR_LBAR_GPIO		0x5140000C
+
+#define GPIOx_OUT_VAL     0x00
+#define GPIOx_OUT_EN      0x04
+#define GPIOx_IN_EN       0x20
+#define GPIOx_INV_EN      0x24
+#define GPIOx_IN_FLTR_EN  0x28
+#define GPIOx_EVNTCNT_EN  0x2C
+#define GPIOx_READ_BACK   0x30
+#define GPIOx_EVNT_EN     0x38
+#define GPIOx_NEGEDGE_EN  0x44
+#define GPIOx_NEGEDGE_STS 0x4C
+#define GPIO_FLT7_AMNT    0xD8
+#define GPIO_MAP_X        0xE0
+#define GPIO_MAP_Y        0xE4
+#define GPIO_FE7_SEL      0xF7
+
+
+/* Status values */
+
+#define DCONSTAT_SCANINT	0
+#define DCONSTAT_SCANINT_DCON	1
+#define DCONSTAT_DISPLAYLOAD	2
+#define DCONSTAT_MISSED		3
+
+/* Source values */
+
+#define DCON_SOURCE_DCON        0
+#define DCON_SOURCE_CPU         1
+
+/* Output values */
+#define DCON_OUTPUT_COLOR       0
+#define DCON_OUTPUT_MONO        1
+
+/* Sleep values */
+#define DCON_ACTIVE             0
+#define DCON_SLEEP              1
+
+/* Interrupt */
+#define DCON_IRQ                6
+
+#endif

drivers/staging/olpc_dcon/olpc_dcon_xo_1.c

+/*
+ * Mainly by David Woodhouse, somewhat modified by Jordan Crouse
+ *
+ * Copyright © 2006-2007  Red Hat, Inc.
+ * Copyright © 2006-2007  Advanced Micro Devices, Inc.
+ * Copyright © 2009       VIA Technology, Inc.
+ * Copyright (c) 2010  Andres Salomon <dilinger@queued.net>
+ *
+ * This program is free software.  You can redistribute it and/or
+ * modify it under the terms of version 2 of the GNU General Public
+ * License as published by the Free Software Foundation.
+ */
+
+#include <asm/olpc.h>
+
+#include "olpc_dcon.h"
+
+/* Base address of the GPIO registers */
+static unsigned long gpio_base;
+
+/*
+ * List of GPIOs that we care about:
+ * (in)  GPIO12   -- DCONBLANK
+ * (in)  GPIO[56] -- DCONSTAT[01]
+ * (out) GPIO11   -- DCONLOAD
+ */
+
+#define IN_GPIOS ((1<<5) | (1<<6) | (1<<7) | (1<<12))
+#define OUT_GPIOS (1<<11)
+
+static int dcon_init_xo_1(void)
+{
+	unsigned long lo, hi;
+	unsigned char lob;
+
+	rdmsr(MSR_LBAR_GPIO, lo, hi);
+
+	/* Check the mask and whether GPIO is enabled (sanity check) */
+	if (hi != 0x0000f001) {
+		printk(KERN_ERR "GPIO not enabled -- cannot use DCON\n");
+		return -ENODEV;
+	}
+
+	/* Mask off the IO base address */
+	gpio_base = lo & 0x0000ff00;
+
+	/* Turn off the event enable for GPIO7 just to be safe */
+	outl(1 << (16+7), gpio_base + GPIOx_EVNT_EN);
+
+	/* Set the directions for the GPIO pins */
+	outl(OUT_GPIOS | (IN_GPIOS << 16), gpio_base + GPIOx_OUT_EN);
+	outl(IN_GPIOS | (OUT_GPIOS << 16), gpio_base + GPIOx_IN_EN);
+
+	/* Set up the interrupt mappings */
+
+	/* Set the IRQ to pair 2 */
+	geode_gpio_event_irq(OLPC_GPIO_DCON_IRQ, 2);
+
+	/* Enable group 2 to trigger the DCON interrupt */
+	geode_gpio_set_irq(2, DCON_IRQ);
+
+	/* Select edge level for interrupt (in PIC) */
+	lob = inb(0x4d0);
+	lob &= ~(1 << DCON_IRQ);
+	outb(lob, 0x4d0);
+
+	/* Register the interupt handler */
+	if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", &dcon_driver))
+		return -EIO;
+
+	/* Clear INV_EN for GPIO7 (DCONIRQ) */
+	outl((1<<(16+7)), gpio_base + GPIOx_INV_EN);
+
+	/* Enable filter for GPIO12 (DCONBLANK) */
+	outl(1<<(12), gpio_base + GPIOx_IN_FLTR_EN);
+
+	/* Disable filter for GPIO7 */
+	outl(1<<(16+7), gpio_base + GPIOx_IN_FLTR_EN);
+
+	/* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+
+	outl(1<<(16+7), gpio_base + GPIOx_EVNTCNT_EN);
+	outl(1<<(16+12), gpio_base + GPIOx_EVNTCNT_EN);
+
+	/* Add GPIO12 to the Filter Event Pair #7 */
+	outb(12, gpio_base + GPIO_FE7_SEL);
+
+	/* Turn off negative Edge Enable for GPIO12 */
+	outl(1<<(16+12), gpio_base + GPIOx_NEGEDGE_EN);
+
+	/* Enable negative Edge Enable for GPIO7 */
+	outl(1<<7, gpio_base + GPIOx_NEGEDGE_EN);
+
+	/* Zero the filter amount for Filter Event Pair #7 */
+	outw(0, gpio_base + GPIO_FLT7_AMNT);
+
+	/* Clear the negative edge status for GPIO7 and GPIO12 */
+	outl((1<<7) | (1<<12), gpio_base+0x4c);
+
+	/* FIXME:  Clear the posiitive status as well, just to be sure */
+	outl((1<<7) | (1<<12), gpio_base+0x48);
+
+	/* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+	outl((1<<(7))|(1<<12), gpio_base + GPIOx_EVNT_EN);
+
+	/* Determine the current state by reading the GPIO bit */
+	/* Earlier stages of the boot process have established the state */
+	dcon_source = inl(gpio_base + GPIOx_OUT_VAL) & (1<<11)
+		? DCON_SOURCE_CPU
+		: DCON_SOURCE_DCON;
+	dcon_pending = dcon_source;
+
+	return 0;
+}
+
+static void dcon_wiggle_xo_1(void)
+{
+	int x;
+
+	/*
+	 * According to HiMax, when powering the DCON up we should hold
+	 * SMB_DATA high for 8 SMB_CLK cycles.  This will force the DCON
+	 * state machine to reset to a (sane) initial state.  Mitch Bradley
+	 * did some testing and discovered that holding for 16 SMB_CLK cycles
+	 * worked a lot more reliably, so that's what we do here.
+	 *
+	 * According to the cs5536 spec, to set GPIO14 to SMB_CLK we must
+	 * simultaneously set AUX1 IN/OUT to GPIO14; ditto for SMB_DATA and
+	 * GPIO15.
+ 	 */
+	geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_VAL);
+	geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_ENABLE);
+	geode_gpio_clear(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);
+	geode_gpio_clear(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX2);
+	geode_gpio_clear(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);
+
+	for (x = 0; x < 16; x++) {
+		udelay(5);
+		geode_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
+		udelay(5);
+		geode_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
+	}
+	udelay(5);
+	geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);
+	geode_gpio_set(OLPC_GPIO_SMB_CLK|OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);
+}
+
+static void dcon_set_dconload_1(int val)
+{
+	if (val)	
+		outl(1<<11, gpio_base + GPIOx_OUT_VAL);
+	else
+		outl(1<<(11 + 16), gpio_base + GPIOx_OUT_VAL);
+}
+
+static int dcon_read_status_xo_1(void)
+{
+	int status = inl(gpio_base + GPIOx_READ_BACK) >> 5;
+	
+	/* Clear the negative edge status for GPIO7 */
+	outl(1 << 7, gpio_base + GPIOx_NEGEDGE_STS);
+
+	return status;
+}
+
+static struct dcon_platform_data dcon_pdata_xo_1 = {
+	.init = dcon_init_xo_1,
+	.bus_stabilize_wiggle = dcon_wiggle_xo_1,
+	.set_dconload = dcon_set_dconload_1,
+	.read_status = dcon_read_status_xo_1,
+};

drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c

+/*
+ * Copyright (c) 2009,2010       One Laptop per Child
+ *
+ * This program is free software.  You can redistribute it and/or
+ * modify it under the terms of version 2 of the GNU General Public
+ * License as published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+
+/* Hardware setup on the XO 1.5:
+ * 	DCONLOAD connects to
+ *		VX855_GPO12 (not nCR_PWOFF)   (rev A)
+ *		VX855_GPIO1 (not SMBCK2)      (rev B)
+ * 	DCONBLANK connects to VX855_GPIO8 (not SSPICLK)  unused in driver
+ *	DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
+ *	DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
+ *	DCONIRQ connects to VX855_GPIO12 (on B3.  on B2, it goes to
+ *		SMBALRT, which doesn't work.)
+ *	DCONSMBDATA connects to VX855 graphics CRTSPD
+ *	DCONSMBCLK connects to VX855 graphics CRTSPCLK
+ */
+
+#define TEST_B2 0   // define to test B3 paths on a modded B2 board
+
+#define VX855_GENL_PURPOSE_OUTPUT 0x44c // PMIO_Rx4c-4f
+#define VX855_GPI_STATUS_CHG 0x450  // PMIO_Rx50
+#define VX855_GPI_SCI_SMI 0x452  // PMIO_Rx52
+#define BIT_GPIO12 0x40
+
+#define PREFIX "OLPC DCON:"
+
+/*
+  there is no support here for DCONIRQ on 1.5 boards earlier than
+  B3.  the issue is that the DCONIRQ signal on earlier boards is
+  routed to SMBALRT, which turns out to to be a level sensitive
+  interrupt.  the DCONIRQ signal is far too short (11usec) to
+  be detected reliably in that case.  including support for
+  DCONIRQ functions no better than none at all.
+*/
+
+static struct dcon_platform_data dcon_pdata_xo_1_5;
+
+static void dcon_clear_irq(void)
+{
+	if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
+		// irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12
+		outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
+	}
+}
+
+static int dcon_was_irq(void)
+{
+	u_int8_t tmp;
+
+	if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
+		// irq status will appear in PMIO_Rx50[6] on gpio12
+		tmp = inb(VX855_GPI_STATUS_CHG);
+		return !!(tmp & BIT_GPIO12);
+	}
+
+	return 0;
+}
+
+static int dcon_init_xo_1_5(void)
+{
+	unsigned int irq;
+	u_int8_t tmp;
+	struct pci_dev *pdev;
+	
+	
+	pdev = pci_get_device(PCI_VENDOR_ID_VIA,
+			      PCI_DEVICE_ID_VIA_VX855, NULL);
+	if (!pdev) {
+		printk(KERN_ERR "cannot find VX855 PCI ID\n");
+		return 1;
+	}
+
+	if (olpc_board_at_least(olpc_board(BOARD_XO_1_5_B1))) {
+		pci_read_config_byte(pdev, 0x95, &tmp);
+		pci_write_config_byte(pdev, 0x95, tmp|0x0c);
+	} else {
+		/* Set GPO12 to GPO mode, not nCR_PWOFF */
+		pci_read_config_byte(pdev, 0x9b, &tmp);
+		pci_write_config_byte(pdev, 0x9b, tmp|0x01);
+	}
+
+	/* Set GPIO8 to GPIO mode, not SSPICLK */
+	pci_read_config_byte(pdev, 0xe3, &tmp);
+	pci_write_config_byte(pdev, 0xe3, tmp | 0x04);
+
+	/* Set GPI10/GPI11 to GPI mode, not SSPISDI/SSPISS */
+	pci_read_config_byte(pdev, 0xe4, &tmp);
+	pci_write_config_byte(pdev, 0xe4, tmp|0x08);
+
+	if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
+		// clear PMU_RxE1[6] to select SCI on GPIO12
+		// clear PMU_RxE0[6] to choose falling edge
+		pci_read_config_byte(pdev, 0xe1, &tmp);
+		pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12);
+		pci_read_config_byte(pdev, 0xe0, &tmp);
+		pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12);
+
+		dcon_clear_irq();
+
+		// set   PMIO_Rx52[6] to enable SCI/SMI on gpio12
+		outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
+
+	}
+
+	/* Determine the current state of DCONLOAD, likely set by firmware */
+	if (olpc_board_at_least(olpc_board(BOARD_XO_1_5_B1))) {
+		// GPIO1
+		dcon_source = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
+			DCON_SOURCE_CPU : DCON_SOURCE_DCON;
+	} else {
+		// GPO12
+		dcon_source = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x04000000) ?
+			DCON_SOURCE_CPU : DCON_SOURCE_DCON;
+	}
+	dcon_pending = dcon_source;
+
+	pci_dev_put(pdev);
+
+	/* we're sharing the IRQ with ACPI */
+	irq = acpi_gbl_FADT.sci_interrupt;
+	if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", &dcon_driver)) {
+		printk(KERN_ERR PREFIX "DCON (IRQ%d) allocation failed\n", irq);
+		return 1;
+	}
+
+
+	return 0;
+}
+
+static void set_i2c_line(int sda, int scl)
+{
+	unsigned char tmp;
+	unsigned int port = 0x26;
+
+	/* FIXME: This directly accesses the CRT GPIO controller !!! */
+	outb(port, 0x3c4);
+	tmp = inb(0x3c5);
+
+	if (scl)
+		tmp |= 0x20;
+	else
+		tmp &= ~0x20;
+
+	if (sda)
+		tmp |= 0x10;
+	else
+		tmp &= ~0x10;
+
+	tmp |= 0x01;
+
+	outb(port, 0x3c4);
+	outb(tmp, 0x3c5);
+}
+
+
+static void dcon_wiggle_xo_1_5(void)
+{
+	int x;
+
+	/*
+	 * According to HiMax, when powering the DCON up we should hold
+	 * SMB_DATA high for 8 SMB_CLK cycles.  This will force the DCON
+	 * state machine to reset to a (sane) initial state.  Mitch Bradley
+	 * did some testing and discovered that holding for 16 SMB_CLK cycles
+	 * worked a lot more reliably, so that's what we do here.
+ 	 */
+	set_i2c_line(1, 1);
+
+	for (x = 0; x < 16; x++) {
+		udelay(5);
+		set_i2c_line(1, 0);
+		udelay(5);
+		set_i2c_line(1, 1);
+	}
+	udelay(5);
+
+	if (TEST_B2 || olpc_board_at_least(olpc_board(BOARD_XO_1_5_B3))) {
+		// set   PMIO_Rx52[6] to enable SCI/SMI on gpio12
+		outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
+	}
+}
+
+static void dcon_set_dconload_xo_1_5(int val)
+{
+	if (olpc_board_at_least(olpc_board(BOARD_XO_1_5_B1))) {
+		gpio_set_value(VX855_GPIO(1), val);
+	} else {
+		gpio_set_value(VX855_GPO(12), val);
+	}
+}
+
+static int dcon_read_status_xo_1_5(void) 
+{
+	int status;
+	
+	if (!dcon_was_irq())
+		return -1;
+
+	// i believe this is the same as "inb(0x44b) & 3"
+	status = gpio_get_value(VX855_GPI(10));
+	status |= gpio_get_value(VX855_GPI(11)) << 1; 
+
+	dcon_clear_irq();
+
+	return status;
+}
+
+static struct dcon_platform_data dcon_pdata_xo_1_5 = {
+	.init = dcon_init_xo_1_5,
+	.bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
+	.set_dconload = dcon_set_dconload_xo_1_5,
+	.read_status = dcon_read_status_xo_1_5,
+};