Commit efa0bf86 authored by Chengming Gui's avatar Chengming Gui Committed by Alex Deucher

drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

add gfxoff_state_changed_by_workload to control gfxoff
when set power_profile_mode
Signed-off-by: default avatarChengming Gui <Jack.Gui@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e0301317
...@@ -92,6 +92,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) ...@@ -92,6 +92,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
hwmgr_set_user_specify_caps(hwmgr); hwmgr_set_user_specify_caps(hwmgr);
hwmgr->fan_ctrl_is_in_default_mode = true; hwmgr->fan_ctrl_is_in_default_mode = true;
hwmgr_init_workload_prority(hwmgr); hwmgr_init_workload_prority(hwmgr);
hwmgr->gfxoff_state_changed_by_workload = false;
switch (hwmgr->chip_family) { switch (hwmgr->chip_family) {
case AMDGPU_FAMILY_CI: case AMDGPU_FAMILY_CI:
......
...@@ -1258,21 +1258,46 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) ...@@ -1258,21 +1258,46 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
return size; return size;
} }
static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
{
struct amdgpu_device *adev = hwmgr->adev;
if ((adev->asic_type == CHIP_RAVEN) &&
(adev->rev_id != 0x15d8) &&
(hwmgr->smu_version >= 0x41e2b))
return true;
else
return false;
}
static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
{ {
int workload_type = 0; int workload_type = 0;
int result = 0;
if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) { if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
pr_err("Invalid power profile mode %ld\n", input[size]); pr_err("Invalid power profile mode %ld\n", input[size]);
return -EINVAL; return -EINVAL;
} }
hwmgr->power_profile_mode = input[size]; if (hwmgr->power_profile_mode == input[size])
return 0;
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = workload_type =
conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode); conv_power_profile_to_pplib_workload(input[size]);
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify, if (workload_type &&
smu10_is_raven1_refresh(hwmgr) &&
!hwmgr->gfxoff_state_changed_by_workload) {
smu10_gfx_off_control(hwmgr, false);
hwmgr->gfxoff_state_changed_by_workload = true;
}
result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1 << workload_type); 1 << workload_type);
if (!result)
hwmgr->power_profile_mode = input[size];
if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
smu10_gfx_off_control(hwmgr, true);
hwmgr->gfxoff_state_changed_by_workload = false;
}
return 0; return 0;
} }
......
...@@ -782,6 +782,7 @@ struct pp_hwmgr { ...@@ -782,6 +782,7 @@ struct pp_hwmgr {
uint32_t workload_mask; uint32_t workload_mask;
uint32_t workload_prority[Workload_Policy_Max]; uint32_t workload_prority[Workload_Policy_Max];
uint32_t workload_setting[Workload_Policy_Max]; uint32_t workload_setting[Workload_Policy_Max];
bool gfxoff_state_changed_by_workload;
}; };
int hwmgr_early_init(struct pp_hwmgr *hwmgr); int hwmgr_early_init(struct pp_hwmgr *hwmgr);
......
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