Commit efebfa80 authored by Shyam Sundar S K's avatar Shyam Sundar S K Committed by Hans de Goede

platform/x86: amd: pmc: provide user message where s0ix is not supported

Some platforms do not support hardware backed s0i3 transitions. When such
CPUs are detected, provide a warning message to the user.
Suggested-by: default avatarSanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: default avatarShyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230412111500.2602529-1-Shyam-sundar.S-k@amd.comReviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent f6e7ac4c
...@@ -94,6 +94,7 @@ ...@@ -94,6 +94,7 @@
#define AMD_CPU_ID_YC 0x14B5 #define AMD_CPU_ID_YC 0x14B5
#define AMD_CPU_ID_CB 0x14D8 #define AMD_CPU_ID_CB 0x14D8
#define AMD_CPU_ID_PS 0x14E8 #define AMD_CPU_ID_PS 0x14E8
#define AMD_CPU_ID_SP 0x14A4
#define PMC_MSG_DELAY_MIN_US 50 #define PMC_MSG_DELAY_MIN_US 50
#define RESPONSE_REGISTER_LOOP_MAX 20000 #define RESPONSE_REGISTER_LOOP_MAX 20000
...@@ -886,6 +887,7 @@ static const struct pci_device_id pmc_pci_ids[] = { ...@@ -886,6 +887,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
{ } { }
}; };
...@@ -964,6 +966,13 @@ static int amd_pmc_probe(struct platform_device *pdev) ...@@ -964,6 +966,13 @@ static int amd_pmc_probe(struct platform_device *pdev)
} }
dev->cpu_id = rdev->device; dev->cpu_id = rdev->device;
if (dev->cpu_id == AMD_CPU_ID_SP) {
dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
err = -ENODEV;
goto err_pci_dev_put;
}
dev->rdev = rdev; dev->rdev = rdev;
err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
if (err) { if (err) {
......
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