Commit efff2e02 authored by Mark Rustad's avatar Mark Rustad Committed by Jeff Kirsher

ixgbe: Correct spec violations by waiting after reset

The ixgbe driver was violating the specification in the datasheet
by not waiting 1ms before checking for the reset bit clearing. This
is called out for devices supported by ixgbe, so implement the
required delay.
Reported-by: default avatarDan Streetman <dan.streetman@canonical.com>
Signed-off-by: default avatarMark Rustad <mark.d.rustad@intel.com>
Tested-by: default avatarDarin Miller <darin.j.miller@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent a9763f3c
/******************************************************************************* /*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver Intel 10 Gigabit PCI Express Linux driver
Copyright(c) 1999 - 2014 Intel Corporation. Copyright(c) 1999 - 2015 Intel Corporation.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
...@@ -765,13 +765,14 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) ...@@ -765,13 +765,14 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
usleep_range(1000, 1200);
/* Poll for reset bit to self-clear indicating reset is complete */ /* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
udelay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST)) if (!(ctrl & IXGBE_CTRL_RST))
break; break;
udelay(1);
} }
if (ctrl & IXGBE_CTRL_RST) { if (ctrl & IXGBE_CTRL_RST) {
status = IXGBE_ERR_RESET_FAILED; status = IXGBE_ERR_RESET_FAILED;
......
...@@ -990,13 +990,14 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) ...@@ -990,13 +990,14 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
usleep_range(1000, 1200);
/* Poll for reset bit to self-clear indicating reset is complete */ /* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
udelay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST_MASK)) if (!(ctrl & IXGBE_CTRL_RST_MASK))
break; break;
udelay(1);
} }
if (ctrl & IXGBE_CTRL_RST_MASK) { if (ctrl & IXGBE_CTRL_RST_MASK) {
......
...@@ -110,13 +110,14 @@ s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) ...@@ -110,13 +110,14 @@ s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
usleep_range(1000, 1200);
/* Poll for reset bit to self-clear indicating reset is complete */ /* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
udelay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST_MASK)) if (!(ctrl & IXGBE_CTRL_RST_MASK))
break; break;
udelay(1);
} }
if (ctrl & IXGBE_CTRL_RST_MASK) { if (ctrl & IXGBE_CTRL_RST_MASK) {
......
...@@ -2146,13 +2146,14 @@ static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) ...@@ -2146,13 +2146,14 @@ static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_FLUSH(hw);
usleep_range(1000, 1200);
/* Poll for reset bit to self-clear meaning reset is complete */ /* Poll for reset bit to self-clear meaning reset is complete */
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
udelay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST_MASK)) if (!(ctrl & IXGBE_CTRL_RST_MASK))
break; break;
udelay(1);
} }
if (ctrl & IXGBE_CTRL_RST_MASK) { if (ctrl & IXGBE_CTRL_RST_MASK) {
......
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