Commit f35235a3 authored by Russell King's avatar Russell King

ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness

Add a dsb after the isb to ensure that the previous writes to the
CP15 registers take effect before we enable the MMU.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 1c0270cd
...@@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume) ...@@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume)
mcr p15, 0, r4, c10, c2, 0 @ write PRRR mcr p15, 0, r4, c10, c2, 0 @ write PRRR
mcr p15, 0, r5, c10, c2, 1 @ write NMRR mcr p15, 0, r5, c10, c2, 1 @ write NMRR
isb isb
dsb
mov r0, r9 @ control register mov r0, r9 @ control register
mov r2, r7, lsr #14 @ get TTB0 base mov r2, r7, lsr #14 @ get TTB0 base
mov r2, r2, lsl #14 mov r2, r2, lsl #14
......
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