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Commit f3a2439f authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'rproc-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux 

Pull remoteproc updates from Bjorn Andersson:

 - Support for PRU clients to acquire a control reference to the PRU
   instances is introduced, and the PRU now allows specifying
   firmware-name in Devicetree. sysfs is requested to be read-only when
   the remoteproc instance is consumed by another kernel driver

 - Support for the C7xv DSP on AM62A SoC is introduced

 - The Devicetree binding for the Qualcomm PAS devices are split up in
   multiple files, to better account for the differences in resources
   between them. A number of missing Devicetree bindings are added, and
   the Qualcomm WCNSS binding is converted to YAML

 - A few cleanups are introduced for the Mediatek SCP driver. And a
   sanity check of the firmware image is introduced in the Mediatek
   driver

 - For Qualcomm SC7280 ADSP support is added, MSM8953 gains ADSP and
   modem support, SM6115 and SM8550 gains ADSP, CDSP and modem support,
   and support for pronto v3 support (used on e.g. MSM8953) is added

 - The Qualcomm modem remoteproc driver is modified to use a no-map
   reserved-memory region for it's authentication metadata, in order to
   avoid fatal security violations caused by accesses from Linux during
   the authentication process

 - Support for separate loading of a Devicetree blob is added to the PAS
   driver, and support for the PAS driver to carve out DSM memory for
   the modem is added as well

 - The Qualcomm ADSP remoteproc driver gains support for mapping memory
   into specific range using the IOMMU. The sysmon driver is
   transitioned to strlcpy()

* tag 'rproc-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (69 commits)
  dt-bindings: mailbox: qcom,apcs-kpss-global: drop mbox-names from example
  dt-bindings: remoteproc: qcom,glink-edge: correct label description
  dt-bindings: remoteproc: qcom,glink-rpm-edge: convert to DT schema
  dt-bindings: remoteproc: qcom,sm8550-pas: correct power domains
  remoteproc: qcom_q6v5_pas: enable sm8550 adsp & cdsp autoboot
  dt-bindings: remoteproc: qcom: Add sm6115 pas yaml file
  remoteproc: qcom: pas: Add sm6115 remoteprocs
  remoteproc: qcom: pas: Adjust the phys addr wrt the mem region
  remoteproc: qcom: fix sparse warnings
  remoteproc: qcom: replace kstrdup with kstrndup
  remoteproc: mediatek: Check the SCP image format
  remoteproc: qcom_q6v5_mss: Use a carveout to authenticate modem headers
  Revert "remoteproc: qcom_q6v5_mss: map/unmap metadata region before/after use"
  dt-bindings: remoteproc: qcom,sc7280-mss-pil: Update memory-region
  dt-bindings: remoteproc: qcom,sc7180-mss-pil: Update memory-region
  dt-bindings: remoteproc: qcom,msm8996-mss-pil: Update memory region
  dt-bindings: remoteproc: qcom,q6v5: Move MSM8996 to schema
  remoteproc: qcom_q6v5_pas: add sm8550 adsp, cdsp & mpss compatible & data
  remoteproc: qcom_q6v5_pas: add support for assigning memory to firmware
  remoteproc: qcom_q6v5_pas: add support for dtb co-firmware loading
  ...
parents cc38a46d 7c855ef7
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Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
View file @ f3a2439f
......@@ -180,7 +180,6 @@ examples:
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
mbox-names = "rpm_hlos";
};
# Example apcs with qcs404
......
Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml
View file @ f3a2439f
......@@ -42,7 +42,9 @@ properties:
maxItems: 1
label:
description: The names of the state bits used for SMP2P output
description:
Name of the edge, used for debugging and identification purposes. The
node name will be used if this is not present.
mboxes:
maxItems: 1
......
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8916 MSS Peripheral Image Loader (and similar)
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description:
This document describes the hardware for a component that loads and boots
firmware on the Qualcomm MSM8916 Modem Hexagon Core (and similar).
properties:
compatible:
oneOf:
- enum:
- qcom,msm8909-mss-pil
- qcom,msm8916-mss-pil
- qcom,msm8953-mss-pil
- qcom,msm8974-mss-pil
- const: qcom,q6v5-pil
description: Deprecated, prefer using qcom,msm8916-mss-pil
deprecated: true
reg:
items:
- description: MSS QDSP6 registers
- description: RMB registers
reg-names:
items:
- const: qdsp6
- const: rmb
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
clocks:
items:
- description: Configuration interface (AXI) clock
- description: Configuration bus (AHB) clock
- description: Boot ROM (AHB) clock
- description: XO proxy clock (control handed over after startup)
clock-names:
items:
- const: iface
- const: bus
- const: mem
- const: xo
power-domains:
items:
- description: CX proxy power domain (control handed over after startup)
- description: MX proxy power domain (control handed over after startup)
- description: MSS proxy power domain (control handed over after startup)
(only valid for qcom,msm8953-mss-pil)
minItems: 2
power-domain-names:
items:
- const: cx
- const: mx
- const: mss # only valid for qcom,msm8953-mss-pil
minItems: 2
pll-supply:
description: PLL proxy supply (control handed over after startup)
mss-supply:
description: MSS power domain supply (only valid for qcom,msm8974-mss-pil)
resets:
items:
- description: MSS restart control
reset-names:
items:
- const: mss_restart
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
items:
- description: Stop modem
qcom,smem-state-names:
description: Names of the states used by the AP to signal the Hexagon core
items:
- const: stop
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Halt registers are used to halt transactions of various sub-components
within MSS.
items:
- items:
- description: phandle to TCSR syscon region
- description: offset to the Q6 halt register
- description: offset to the modem halt register
- description: offset to the nc halt register
memory-region:
items:
- description: MBA reserved region
- description: MPSS reserved region
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
items:
- description: Name of MBA firmware
- description: Name of modem firmware
bam-dmux:
$ref: /schemas/net/qcom,bam-dmux.yaml#
description:
Qualcomm BAM Data Multiplexer (provides network interface to the modem)
smd-edge:
$ref: qcom,smd-edge.yaml#
description:
Qualcomm SMD subnode which represents communication edge, channels
and devices related to the DSP.
properties:
label:
enum:
- modem
- hexagon
unevaluatedProperties: false
# Deprecated properties
cx-supply:
description: CX power domain regulator supply (prefer using power-domains)
deprecated: true
mx-supply:
description: MX power domain regulator supply (prefer using power-domains)
deprecated: true
mba:
type: object
description:
MBA reserved region (prefer using memory-region with two items)
properties:
memory-region: true
required:
- memory-region
deprecated: true
mpss:
type: object
description:
MPSS reserved region (prefer using memory-region with two items)
properties:
memory-region: true
required:
- memory-region
deprecated: true
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
- pll-supply
- resets
- reset-names
- qcom,halt-regs
- qcom,smem-states
- qcom,smem-state-names
- smd-edge
allOf:
- if:
properties:
compatible:
const: qcom,msm8953-mss-pil
then:
properties:
power-domains:
minItems: 3
power-domain-names:
minItems: 3
required:
- power-domains
- power-domain-names
else:
properties:
power-domains:
maxItems: 2
power-domain-names:
maxItems: 2
- if:
properties:
compatible:
const: qcom,msm8974-mss-pil
then:
required:
- mss-supply
else:
properties:
mss-supply: false
# Fallbacks for deprecated properties
- oneOf:
- required:
- memory-region
- required:
- mba
- mpss
- oneOf:
- required:
- power-domains
- power-domain-names
- required:
- cx-supply
- mx-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,msm8916-mss-pil";
reg = <0x04080000 0x100>, <0x04020000 0x40>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
<&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
qcom,smem-states = <&hexagon_smp2p_out 0>;
qcom,smem-state-names = "stop";
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&xo_board>;
clock-names = "iface", "bus", "mem", "xo";
power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>;
power-domain-names = "cx", "mx";
pll-supply = <&pm8916_l7>;
resets = <&scm 0>;
reset-names = "mss_restart";
memory-region = <&mba_mem>, <&mpss_mem>;
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
qcom,ipc = <&apcs 8 12>;
qcom,remote-pid = <1>;
label = "hexagon";
};
};
Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,pas-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Peripheral Authentication Service Common Properties
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Common properties of Qualcomm SoCs Peripheral Authentication Service.
properties:
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
interconnects:
maxItems: 1
interrupts:
minItems: 5
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
interrupt-names:
minItems: 5
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
power-domains:
minItems: 1
maxItems: 3
power-domain-names:
minItems: 1
maxItems: 3
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
items:
- description: Stop the modem
qcom,smem-state-names:
description: The names of the state bits used for SMP2P output
items:
- const: stop
smd-edge:
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
description:
Qualcomm Shared Memory subnode which represents communication edge,
channels and devices related to the ADSP.
unevaluatedProperties: false
glink-edge:
$ref: /schemas/remoteproc/qcom,glink-edge.yaml#
description:
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the ADSP.
unevaluatedProperties: false
required:
- clocks
- clock-names
- interrupts
- interrupt-names
- memory-region
- qcom,smem-states
- qcom,smem-state-names
additionalProperties: true
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
View file @ f3a2439f
......@@ -7,14 +7,8 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,q6v5-pil",
"qcom,ipq8074-wcss-pil"
"qcom,qcs404-wcss-pil"
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
"qcom,msm8998-mss-pil"
"qcom,sdm845-mss-pil"
- reg:
Usage: required
......@@ -35,26 +29,7 @@ on the Qualcomm Hexagon core.
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: The interrupts needed depends on the compatible
string:
qcom,q6v5-pil:
qcom,ipq8074-wcss-pil:
qcom,qcs404-wcss-pil:
qcom,msm8916-mss-pil:
qcom,msm8974-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack"
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
qcom,sdm845-mss-pil:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
- firmware-name:
Usage: optional
Value type: <stringlist>
Definition: must list the relative firmware image paths for mba and
modem. They are used for booting and authenticating the
Hexagon core.
Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
- clocks:
Usage: required
......@@ -72,67 +47,23 @@ on the Qualcomm Hexagon core.
"gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc",
"lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc",
"lcc_axim_cbc", "lcc_bcr_sleep"
qcom,q6v5-pil:
qcom,msm8916-mss-pil:
qcom,msm8974-mss-pil:
must be "iface", "bus", "mem", "xo"
qcom,msm8996-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "pnoc", "qdss"
qcom,msm8998-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "qdss"
qcom,sdm845-mss-pil:
must be "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng"
- resets:
Usage: required
Value type: <phandle>
Definition: reference to the reset-controller for the modem sub-system
reference to the list of 3 reset-controllers for the
Definition: reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
sub-system on SDM845 SoCs
- reset-names:
Usage: required
Value type: <stringlist>
Definition: must be "mss_restart" for the modem sub-system
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
sub-system on SDM845 SoCs
For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
- memory-region:
Usage: required
Value type: <phandle>
Definition: reference to the reserved-memory for the mba region followed
by the mpss region
For the compatible strings below the following supplies are required:
"qcom,q6v5-pil"
"qcom,msm8916-mss-pil",
- cx-supply: (deprecated, use power domain instead)
- mx-supply: (deprecated, use power domain instead)
- pll-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the Hexagon core
For the compatible string below the following supplies are required:
"qcom,msm8974-mss-pil"
- cx-supply: (deprecated, use power domain instead)
- mss-supply:
- mx-supply: (deprecated, use power domain instead)
- pll-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the Hexagon core
Definition: reference to wcss reserved-memory region.
For the compatible string below the following supplies are required:
"qcom,qcs404-wcss-pil"
......@@ -142,39 +73,6 @@ For the compatible string below the following supplies are required:
Definition: reference to the regulators to be held on behalf of the
booting of the Hexagon core
For the compatible string below the following supplies are required:
"qcom,msm8996-mss-pil"
- pll-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the Hexagon core
- power-domains:
Usage: required
Value type: <phandle>
Definition: reference to power-domains that match power-domain-names
- power-domain-names:
Usage: required
Value type: <stringlist>
Definition: The power-domains needed depend on the compatible string:
qcom,ipq8074-wcss-pil:
no power-domain names required
qcom,q6v5-pil:
qcom,msm8916-mss-pil:
qcom,msm8974-mss-pil:
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
must be "cx", "mx"
qcom,sdm845-mss-pil:
must be "cx", "mx", "mss"
- qcom,qmp:
Usage: optional
Value type: <phandle>
Definition: reference to the AOSS side-channel message RAM.
- qcom,smem-states:
Usage: required
Value type: <phandle>
......@@ -190,16 +88,9 @@ For the compatible string below the following supplies are required:
Usage: required
Value type: <prop-encoded-array>
Definition: a phandle reference to a syscon representing TCSR followed
by the three offsets within syscon for q6, modem and nc
by the three offsets within syscon for q6, wcss and nc
halt registers.
The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.
= SUBNODES:
The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
the memory regions used by the Hexagon firmware. Each sub-node must contain:
- memory-region:
Usage: required
Value type: <phandle>
......@@ -209,56 +100,3 @@ The Hexagon node may also have an subnode named either "smd-edge" or
"glink-edge" that describes the communication edge, channels and devices
related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and
../soc/qcom/qcom,glink.txt for details on how to describe these.
= EXAMPLE
The following example describes the resources needed to boot control the
Hexagon, as it is found on MSM8974 boards.
remoteproc@fc880000 {
compatible = "qcom,msm8974-mss-pil";
reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&xo_board>;
clock-names = "iface", "bus", "mem", "xo";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
mba {
memory-region = <&mba_region>;
};
mpss {
memory-region = <&mpss_region>;
};
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 12>;
qcom,smd-edge = <0>;
label = "modem";
};
};
Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QCS404 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm QCS404 SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,qcs404-adsp-pas
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
power-domains: false
power-domain-names: false
smd-edge: false
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
remoteproc@c700000 {
compatible = "qcom,qcs404-adsp-pas";
reg = <0x0c700000 0x4040>;
clocks = <&xo_board>;
clock-names = "xo";
interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
memory-region = <&adsp_fw_mem>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
qcom,remote-pid = <2>;
mboxes = <&apcs_glb 8>;
label = "adsp";
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml
View file @ f3a2439f
......@@ -95,6 +95,7 @@ properties:
items:
- description: MBA reserved region
- description: modem reserved region
- description: metadata reserved region
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
......@@ -223,7 +224,7 @@ examples:
<&rpmhpd SC7180_MSS>;
power-domain-names = "cx", "mx", "mss";
memory-region = <&mba_mem>, <&mpss_mem>;
memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
qcom,qmp = <&aoss_qmp>;
......
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7180/SC7280 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sc7180-mpss-pas
- qcom,sc7280-mpss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
interrupts:
minItems: 6
interrupt-names:
minItems: 6
power-domains:
minItems: 2
items:
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
minItems: 2
items:
- const: cx
- const: mx
- const: mss
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
smd-edge: false
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sc7180-mpss-pas
then:
properties:
power-domains:
minItems: 3
power-domain-names:
minItems: 3
else:
properties:
power-domains:
maxItems: 2
power-domain-names:
maxItems: 2
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@4080000 {
compatible = "qcom,sc7180-mpss-pas";
reg = <0x04080000 0x4040>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
memory-region = <&mpss_mem>;
power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
<&rpmhpd SC7180_MSS>;
power-domain-names = "cx", "mx", "mss";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apss_shared 12>;
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7280 ADSP Peripheral Image Loader
maintainers:
- Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
description:
This document describes the hardware for a component that loads and boots firmware
on the Qualcomm Technology Inc. ADSP.
properties:
compatible:
enum:
- qcom,sc7280-adsp-pil
reg:
items:
- description: qdsp6ss register
- description: efuse q6ss register
iommus:
items:
- description: Phandle to apps_smmu node with sid mask
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
clocks:
items:
- description: XO clock
- description: GCC CFG NOC LPASS clock
clock-names:
items:
- const: xo
- const: gcc_cfg_noc_lpass
power-domains:
items:
- description: LCX power domain
resets:
items:
- description: PDC AUDIO SYNC RESET
- description: CC LPASS restart
reset-names:
items:
- const: pdc_sync
- const: cc_lpass
memory-region:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Phandle reference to a syscon representing TCSR followed by the
four offsets within syscon for q6, modem, nc and qv6 halt registers.
items:
- items:
- description: phandle to TCSR_MUTEX registers
- description: offset to the Q6 halt register
- description: offset to the modem halt register
- description: offset to the nc halt register
- description: offset to the vq6 halt register
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
items:
- description: Stop the modem
qcom,smem-state-names:
description: The names of the state bits used for SMP2P output
const: stop
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
glink-edge:
$ref: qcom,glink-edge.yaml#
type: object
unevaluatedProperties: false
description: |
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the ADSP.
properties:
label:
const: lpass
gpr: true
apr: false
fastrpc: false
required:
- label
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- power-domains
- resets
- reset-names
- qcom,halt-regs
- memory-region
- qcom,smem-states
- qcom,smem-state-names
- qcom,qmp
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
remoteproc@3000000 {
compatible = "qcom,sc7280-adsp-pil";
reg = <0x03000000 0x5000>,
<0x0355b000 0x10>;
interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack", "shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "xo", "gcc_cfg_noc_lpass";
power-domains = <&rpmhpd SC7280_LCX>;
resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
<&aoss_reset AOSS_CC_LPASS_RESTART>;
reset-names = "pdc_sync", "cc_lpass";
qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
memory-region = <&adsp_mem>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
qcom,qmp = <&aoss_qmp>;
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
View file @ f3a2439f
......@@ -95,6 +95,7 @@ properties:
items:
- description: MBA reserved region
- description: modem reserved region
- description: metadata reserved region
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
......@@ -240,7 +241,7 @@ examples:
<&rpmhpd SC7280_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mba_mem>, <&mpss_mem>;
memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
qcom,qmp = <&aoss_qmp>;
......
Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC8180X Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
smd-edge: false
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
- if:
properties:
compatible:
enum:
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
then:
properties:
power-domains:
items:
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
else:
properties:
# TODO: incomplete
power-domains: false
power-domain-names: false
unevaluatedProperties: false
Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC8280XP Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SC8280XP SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sc8280xp-adsp-pas
- qcom,sc8280xp-nsp0-pas
- qcom,sc8280xp-nsp1-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
smd-edge: false
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sc8280xp-nsp0-pas
- qcom,sc8280xp-nsp1-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
- if:
properties:
compatible:
enum:
- qcom,sc8280xp-adsp-pas
then:
properties:
power-domains:
items:
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
else:
properties:
power-domains:
items:
- description: NSP power domain
power-domain-names:
items:
- const: nsp
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0x03000000 0x100>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack", "shutdown-ack";
memory-region = <&pil_adsp_mem>;
power-domains = <&rpmhpd SC8280XP_LCX>,
<&rpmhpd SC8280XP_LMX>;
power-domain-names = "lcx", "lmx";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sdx55-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDX55 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SDX55 SoC Peripheral Authentication Service loads and boots firmware
on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sdx55-mpss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
interrupts:
minItems: 6
interrupt-names:
minItems: 6
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
smd-edge: false
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@4080000 {
compatible = "qcom,sdx55-mpss-pas";
reg = <0x04080000 0x4040>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
memory-region = <&mpss_adsp_mem>;
power-domains = <&rpmhpd SDX55_CX>, <&rpmhpd SDX55_MSS>;
power-domain-names = "cx", "mss";
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
label = "mpss";
mboxes = <&apcs 15>;
qcom,remote-pid = <1>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sm6115-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6115 Peripheral Authentication Service
maintainers:
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
description:
Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sm6115-adsp-pas
- qcom,sm6115-cdsp-pas
- qcom,sm6115-mpss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
smd-edge: false
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sm6115-adsp-pas
- qcom,sm6115-cdsp-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
- if:
properties:
compatible:
enum:
- qcom,sm6115-cdsp-pas
- qcom,sm6115-mpss-pas
then:
properties:
power-domains:
items:
- description: CX power domain
power-domain-names:
items:
- const: cx
- if:
properties:
compatible:
enum:
- qcom,sm6115-adsp-pas
then:
properties:
power-domains:
items:
- description: LPI CX power domain
- description: LPI MX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@ab00000 {
compatible = "qcom,sm6115-adsp-pas";
reg = <0x0ab00000 0x100>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
firmware-name = "qcom/sm6115/adsp.mdt";
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
memory-region = <&pil_adsp_mem>;
power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
<&rpmpd SM6115_VDD_LPI_MX>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
qcom,remote-pid = <2>;
mboxes = <&apcs_glb 8>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6350 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SM6350 SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sm6350-adsp-pas
- qcom,sm6350-cdsp-pas
- qcom,sm6350-mpss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
smd-edge: false
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sm6350-adsp-pas
- qcom,sm6350-cdsp-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
- if:
properties:
compatible:
enum:
- qcom,sm6350-adsp-pas
then:
properties:
power-domains:
items:
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
- if:
properties:
compatible:
enum:
- qcom,sm6350-cdsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MX power domain
power-domain-names:
items:
- const: cx
- const: mx
- if:
properties:
compatible:
enum:
- qcom,sm6350-mpss-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@3000000 {
compatible = "qcom,sm6350-adsp-pas";
reg = <0x03000000 0x100>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
memory-region = <&pil_adsp_mem>;
power-domains = <&rpmhpd SM6350_LCX>,
<&rpmhpd SM6350_LMX>;
power-domain-names = "lcx", "lmx";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8150/SM8250 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SM8150/SM8250 SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
- qcom,sm8150-mpss-pas
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-cdsp-pas
- qcom,sm8250-slpi-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
smd-edge: false
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-cdsp-pas
- qcom,sm8250-slpi-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
- if:
properties:
compatible:
enum:
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
- qcom,sm8250-cdsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
power-domain-names:
items:
- const: cx
- if:
properties:
compatible:
enum:
- qcom,sm8150-mpss-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
- if:
properties:
compatible:
enum:
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-slpi-pas
then:
properties:
power-domains:
items:
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@17300000 {
compatible = "qcom,sm8150-adsp-pas";
reg = <0x17300000 0x4040>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
firmware-name = "qcom/sm8150/adsp.mbn";
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
memory-region = <&adsp_mem>;
power-domains = <&rpmhpd SM8150_CX>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
qcom,remote-pid = <2>;
mboxes = <&apss_shared 8>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350/SM8450 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots
firmware on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sm8350-adsp-pas
- qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas
- qcom,sm8350-mpss-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-cdsp-pas
- qcom,sm8450-mpss-pas
- qcom,sm8450-slpi-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
smd-edge: false
memory-region:
minItems: 1
description: Reference to the reserved-memory for the Hexagon core
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sm8350-adsp-pas
- qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-cdsp-pas
- qcom,sm8450-slpi-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
- if:
properties:
compatible:
enum:
- qcom,sm8350-mpss-pas
- qcom,sm8450-mpss-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
- if:
properties:
compatible:
enum:
- qcom,sm8350-adsp-pas
- qcom,sm8350-slpi-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-slpi-pas
then:
properties:
power-domains:
items:
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
- if:
properties:
compatible:
enum:
- qcom,sm8350-cdsp-pas
- qcom,sm8450-cdsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MXC power domain
power-domain-names:
items:
- const: cx
- const: mxc
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
remoteproc@30000000 {
compatible = "qcom,sm8450-adsp-pas";
reg = <0x030000000 0x100>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
firmware-name = "qcom/sm8450/adsp.mbn";
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
memory-region = <&adsp_mem>;
power-domains = <&rpmhpd SM8450_LCX>,
<&rpmhpd SM8450_LMX>;
power-domain-names = "lcx", "lmx";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8550 Peripheral Authentication Service
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware
on the Qualcomm DSP Hexagon cores.
properties:
compatible:
enum:
- qcom,sm8550-adsp-pas
- qcom,sm8550-cdsp-pas
- qcom,sm8550-mpss-pas
reg:
maxItems: 1
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.
smd-edge: false
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
items:
- description: Firmware name of the Hexagon core
- description: Firmware name of the Hexagon Devicetree
memory-region:
minItems: 2
items:
- description: Memory region for main Firmware authentication
- description: Memory region for Devicetree Firmware authentication
- description: DSM Memory region
required:
- compatible
- reg
allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,sm8550-adsp-pas
- qcom,sm8550-cdsp-pas
then:
properties:
interrupts:
maxItems: 5
interrupt-names:
maxItems: 5
memory-region:
maxItems: 2
else:
properties:
interrupts:
minItems: 6
interrupt-names:
minItems: 6
memory-region:
minItems: 3
- if:
properties:
compatible:
enum:
- qcom,sm8550-adsp-pas
then:
properties:
power-domains:
items:
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: lcx
- const: lmx
- if:
properties:
compatible:
enum:
- qcom,sm8550-mpss-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
- if:
properties:
compatible:
enum:
- qcom,sm8550-cdsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MXC power domain
- description: NSP power domain
power-domain-names:
items:
- const: cx
- const: mxc
- const: nsp
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
remoteproc@30000000 {
compatible = "qcom,sm8550-adsp-pas";
reg = <0x030000000 0x100>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
memory-region = <&adsp_mem>, <&dtb_adsp_mem>;
firmware-name = "qcom/sm8550/adsp.mbn",
"qcom/sm8550/adsp_dtb.mbn";
power-domains = <&rpmhpd_sm8550_lcx>,
<&rpmhpd_sm8550_lmx>;
power-domain-names = "lcx", "lmx";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
/* ... */
};
};
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt deleted 100644 → 0
View file @ cc38a46d
Qualcomm WCNSS Peripheral Image Loader
This document defines the binding for a component that loads and boots firmware
on the Qualcomm WCNSS core.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,riva-pil",
"qcom,pronto-v1-pil",
"qcom,pronto-v2-pil"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: must specify the base address and size of the CCU, DXE and
PMU register blocks
- reg-names:
Usage: required
Value type: <stringlist>
Definition: must be "ccu", "dxe", "pmu"
- interrupts-extended:
Usage: required
Value type: <prop-encoded-array>
Definition: must list the watchdog and fatal IRQs and may specify the
ready, handover and stop-ack IRQs
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: should be "wdog", "fatal", optionally followed by "ready",
"handover", "stop-ack"
- firmware-name:
Usage: optional
Value type: <string>
Definition: must list the relative firmware image path for the
WCNSS core. Defaults to "wcnss.mdt".
- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddpx-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the WCNSS core
- power-domains:
Usage: required (for qcom,pronto-v1/2-pil)
Value type: <phandle>
Definition: reference to the power domains to be held on behalf of the
booting of the WCNSS core
- power-domain-names:
Usage: required (for qcom,pronto-v1/2-pil)
Value type: <stringlist>
Definition: must be "cx", "mx"
- qcom,smem-states:
Usage: optional
Value type: <prop-encoded-array>
Definition: reference to the SMEM state used to indicate to WCNSS that
it should shut down
- qcom,smem-state-names:
Usage: optional
Value type: <stringlist>
Definition: should be "stop"
- memory-region:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to reserved-memory node for the remote processor
see ../reserved-memory/reserved-memory.txt
= SUBNODES
A required subnode of the WCNSS PIL is used to describe the attached rf module
and its resource dependencies. It is described by the following properties:
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,wcn3620",
"qcom,wcn3660",
"qcom,wcn3660b",
"qcom,wcn3680"
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the xo clock and optionally the rf clock
- clock-names:
Usage: required
Value type: <stringlist>
Definition: should be "xo", optionally followed by "rf"
- vddxo-supply:
- vddrfa-supply:
- vddpa-supply:
- vdddig-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the WCNSS core
The wcnss node can also have an subnode named "smd-edge" that describes the SMD
edge, channels and devices related to the WCNSS.
See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge.
= EXAMPLE
The following example describes the resources needed to boot control the WCNSS,
with attached WCN3680, as it is commonly found on MSM8974 boards.
pronto@fb204000 {
compatible = "qcom,pronto-v2-pil";
reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
interrupts-extended = <&intc 0 149 1>,
<&wcnss_smp2p_slave 0 0>,
<&wcnss_smp2p_slave 1 0>,
<&wcnss_smp2p_slave 2 0>,
<&wcnss_smp2p_slave 3 0>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
power-domains = <&rpmpd MSM8974_VDDCX>, <&rpmpd MSM8974_VDDMX>;
power-domain-names = "cx", "mx";
vddpx-supply = <&pm8941_s3>;
qcom,smem-states = <&wcnss_smp2p_out 0>;
qcom,smem-state-names = "stop";
memory-region = <&wcnss_region>;
pinctrl-names = "default";
pinctrl-0 = <&wcnss_pin_a>;
iris {
compatible = "qcom,wcn3680";
clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>;
clock-names = "xo", "rf";
vddxo-supply = <&pm8941_l6>;
vddrfa-supply = <&pm8941_l11>;
vddpa-supply = <&pm8941_l19>;
vdddig-supply = <&pm8941_s3>;
};
smd-edge {
interrupts = <0 142 1>;
qcom,ipc = <&apcs 8 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
label = "pronto";
wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
qcom,mmio = <&pronto>;
bt {
compatible = "qcom,wcnss-bt";
};
};
};
};
Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm WCNSS Peripheral Image Loader
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description:
This document defines the binding for a component that loads and boots
firmware on the Qualcomm WCNSS core.
properties:
compatible:
description:
Append "qcom,pronto" if the device is actually pronto, and not riva
oneOf:
- items:
- enum:
- qcom,pronto-v1-pil
- qcom,pronto-v2-pil
- qcom,pronto-v3-pil
- const: qcom,pronto
- const: qcom,riva-pil
reg:
maxItems: 3
description:
The base address and size of the CCU, DXE and PMU register blocks
reg-names:
items:
- const: ccu
- const: dxe
- const: pmu
interrupts:
minItems: 2
maxItems: 5
interrupt-names:
minItems: 2
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description:
Relative firmware image path for the WCNSS core. Defaults to
"wcnss.mdt".
vddpx-supply:
description:
PX regulator to be held on behalf of the booting of the WCNSS core
vddmx-supply:
description:
MX regulator to be held on behalf of the booting of the WCNSS core.
vddcx-supply:
description:
CX regulator to be held on behalf of the booting of the WCNSS core.
power-domains:
maxItems: 2
power-domain-names:
items:
- const: cx
- const: mx
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
States used by the AP to signal the WCNSS core that it should shutdown
items:
- description: Stop the modem
qcom,smem-state-names:
description: The names of the state bits used for SMP2P output
items:
- const: stop
memory-region:
maxItems: 1
description: reserved-memory for the WCNSS core
smd-edge:
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
description:
Qualcomm Shared Memory subnode which represents communication edge,
channels and devices related to the ADSP.
iris:
type: object
description:
The iris subnode of the WCNSS PIL is used to describe the attached RF module
and its resource dependencies.
properties:
compatible:
enum:
- qcom,wcn3620
- qcom,wcn3660
- qcom,wcn3660b
- qcom,wcn3680
clocks:
minItems: 1
items:
- description: XO clock
- description: RF clock
clock-names:
minItems: 1
items:
- const: xo
- const: rf
vddxo-supply:
description:
Reference to the regulator to be held on behalf of the booting WCNSS
core
vddrfa-supply:
description:
Reference to the regulator to be held on behalf of the booting WCNSS
core
vddpa-supply:
description:
Reference to the regulator to be held on behalf of the booting WCNSS
core
vdddig-supply:
description:
Reference to the regulator to be held on behalf of the booting WCNSS
core
required:
- compatible
- clocks
- clock-names
- vddxo-supply
- vddrfa-supply
- vddpa-supply
- vdddig-supply
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- iris
- vddpx-supply
- memory-region
- smd-edge
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: qcom,riva-pil
then:
required:
- vddcx-supply
- vddmx-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,pronto-v1-pil
- qcom,pronto-v2-pil
then:
properties:
vddmx-supply:
deprecated: true
description: Deprecated for qcom,pronto-v1/2-pil
vddcx-supply:
deprecated: true
description: Deprecated for qcom,pronto-v1/2-pil
oneOf:
- required:
- power-domains
- power-domain-names
- required:
- vddmx-supply
- vddcx-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,pronto-v3-pil
then:
properties:
vddmx-supply: false
vddcx-supply: false
required:
- power-domains
- power-domain-names
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
pronto@a21b000 {
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>;
power-domain-names = "cx", "mx";
vddpx-supply = <&pm8916_l7>;
qcom,smem-states = <&wcnss_smp2p_out 0>;
qcom,smem-state-names = "stop";
memory-region = <&wcnss_region>;
pinctrl-names = "default";
pinctrl-0 = <&wcnss_pin_a>;
iris {
compatible = "qcom,wcn3620";
vddxo-supply = <&pm8916_l7>;
vddrfa-supply = <&pm8916_s3>;
vddpa-supply = <&pm8916_l9>;
vdddig-supply = <&pm8916_l5>;
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
clock-names = "xo";
};
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
label = "pronto";
wcnss_ctrl: wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
qcom,mmio = <&pronto>;
bluetooth {
compatible = "qcom,wcnss-bt";
};
wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
qcom,smem-state-names = "tx-enable", "tx-rings-empty";
};
};
};
};
Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
View file @ f3a2439f
......@@ -31,10 +31,12 @@ allOf:
properties:
compatible:
enum:
- ti,am62a-c7xv-dsp
- ti,j721e-c66-dsp
- ti,j721e-c71-dsp
- ti,j721s2-c71-dsp
description:
Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs
Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs
......@@ -109,6 +111,7 @@ else:
properties:
compatible:
enum:
- ti,am62a-c7xv-dsp
- ti,j721e-c71-dsp
- ti,j721s2-c71-dsp
then:
......
Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml 0 → 100644
View file @ f3a2439f
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common TI PRU Consumer Binding
maintainers:
- Suman Anna <s-anna@ti.com>
description: |
A PRU application/consumer/user node typically uses one or more PRU device
nodes to implement a PRU application/functionality. Each application/client
node would need a reference to at least a PRU node, and optionally define
some properties needed for hardware/firmware configuration. The below
properties are a list of common properties supported by the PRU remoteproc
infrastructure.
The application nodes shall define their own bindings like regular platform
devices, so below are in addition to each node's bindings.
properties:
ti,prus:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: phandles to the PRU, RTU or Tx_PRU nodes used
minItems: 1
maxItems: 6
items:
maxItems: 1
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
minItems: 1
maxItems: 6
description: |
firmwares for the PRU cores, the default firmware for the core from
the PRU node will be used if not provided. The firmware names should
correspond to the PRU cores listed in the 'ti,prus' property
ti,pruss-gp-mux-sel:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
items:
enum: [0, 1, 2, 3, 4]
description: |
array of values for the GP_MUX_SEL under PRUSS_GPCFG register for a PRU.
This selects the internal muxing scheme for the PRU instance. Values
should correspond to the PRU cores listed in the 'ti,prus' property. The
GP_MUX_SEL setting is a per-slice setting (one setting for PRU0, RTU0,
and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
same slice in the associative array. If the array size is smaller than
the size of 'ti,prus' property, the default out-of-reset value (0) for the
PRU core is used.
required:
- ti,prus
additionalProperties: true
drivers/remoteproc/mtk_scp.c
View file @ f3a2439f
......@@ -649,6 +649,7 @@ static const struct rproc_ops scp_ops = {
.load = scp_load,
.da_to_va = scp_da_to_va,
.parse_fw = scp_parse_fw,
.sanity_check = rproc_elf_sanity_check,
};
/**
......
drivers/remoteproc/mtk_scp_ipi.c
View file @ f3a2439f
......@@ -6,13 +6,17 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/time64.h>
#include <linux/remoteproc/mtk_scp.h>
#include "mtk_common.h"
#define SCP_TIMEOUT_US (2000 * USEC_PER_MSEC)
/**
* scp_ipi_register() - register an ipi function
*
......@@ -156,7 +160,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
unsigned int wait)
{
struct mtk_share_obj __iomem *send_obj = scp->send_buf;
unsigned long timeout;
u32 val;
int ret;
if (WARN_ON(id <= SCP_IPI_INIT) || WARN_ON(id >= SCP_IPI_MAX) ||
......@@ -164,23 +168,21 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
WARN_ON(len > sizeof(send_obj->share_buf)) || WARN_ON(!buf))
return -EINVAL;
mutex_lock(&scp->send_lock);
ret = clk_prepare_enable(scp->clk);
if (ret) {
dev_err(scp->dev, "failed to enable clock\n");
goto unlock_mutex;
return ret;
}
mutex_lock(&scp->send_lock);
/* Wait until SCP receives the last command */
timeout = jiffies + msecs_to_jiffies(2000);
do {
if (time_after(jiffies, timeout)) {
dev_err(scp->dev, "%s: IPI timeout!\n", __func__);
ret = -ETIMEDOUT;
goto clock_disable;
}
} while (readl(scp->reg_base + scp->data->host_to_scp_reg));
ret = readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_reg,
val, !val, 0, SCP_TIMEOUT_US);
if (ret) {
dev_err(scp->dev, "%s: IPI timeout!\n", __func__);
goto unlock_mutex;
}
scp_memcpy_aligned(send_obj->share_buf, buf, len);
......@@ -194,10 +196,9 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
if (wait) {
/* wait for SCP's ACK */
timeout = msecs_to_jiffies(wait);
ret = wait_event_timeout(scp->ack_wq,
scp->ipi_id_ack[id],
timeout);
msecs_to_jiffies(wait));
scp->ipi_id_ack[id] = false;
if (WARN(!ret, "scp ipi %d ack time out !", id))
ret = -EIO;
......@@ -205,10 +206,9 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len,
ret = 0;
}
clock_disable:
clk_disable_unprepare(scp->clk);
unlock_mutex:
mutex_unlock(&scp->send_lock);
clk_disable_unprepare(scp->clk);
return ret;
}
......
drivers/remoteproc/pru_rproc.c
View file @ f3a2439f
......@@ -2,12 +2,14 @@
/*
* PRU-ICSS remoteproc driver for various TI SoCs
*
* Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2014-2022 Texas Instruments Incorporated - https://www.ti.com/
*
* Author(s):
* Suman Anna <s-anna@ti.com>
* Andrew F. Davis <afd@ti.com>
* Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
* Puranjay Mohan <p-mohan@ti.com>
* Md Danish Anwar <danishanwar@ti.com>
*/
#include <linux/bitops.h>
......@@ -16,6 +18,7 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/remoteproc/pruss.h>
#include <linux/pruss_driver.h>
#include <linux/remoteproc.h>
......@@ -111,10 +114,13 @@ struct pru_private_data {
* @rproc: remoteproc pointer for this PRU core
* @data: PRU core specific data
* @mem_regions: data for each of the PRU memory regions
* @client_np: client device node
* @lock: mutex to protect client usage
* @fw_name: name of firmware image used during loading
* @mapped_irq: virtual interrupt numbers of created fw specific mapping
* @pru_interrupt_map: pointer to interrupt mapping description (firmware)
* @pru_interrupt_map_sz: pru_interrupt_map size
* @rmw_lock: lock for read, modify, write operations on registers
* @dbg_single_step: debug state variable to set PRU into single step mode
* @dbg_continuous: debug state variable to restore PRU execution mode
* @evt_count: number of mapped events
......@@ -126,10 +132,13 @@ struct pru_rproc {
struct rproc *rproc;
const struct pru_private_data *data;
struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
struct device_node *client_np;
struct mutex lock;
const char *fw_name;
unsigned int *mapped_irq;
struct pru_irq_rsc *pru_interrupt_map;
size_t pru_interrupt_map_sz;
spinlock_t rmw_lock;
u32 dbg_single_step;
u32 dbg_continuous;
u8 evt_count;
......@@ -146,6 +155,212 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
}
static inline
void pru_control_set_reg(struct pru_rproc *pru, unsigned int reg,
u32 mask, u32 set)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&pru->rmw_lock, flags);
val = pru_control_read_reg(pru, reg);
val &= ~mask;
val |= (set & mask);
pru_control_write_reg(pru, reg, val);
spin_unlock_irqrestore(&pru->rmw_lock, flags);
}
/**
* pru_rproc_set_firmware() - set firmware for a PRU core
* @rproc: the rproc instance of the PRU
* @fw_name: the new firmware name, or NULL if default is desired
*
* Return: 0 on success, or errno in error case.
*/
static int pru_rproc_set_firmware(struct rproc *rproc, const char *fw_name)
{
struct pru_rproc *pru = rproc->priv;
if (!fw_name)
fw_name = pru->fw_name;
return rproc_set_firmware(rproc, fw_name);
}
static struct rproc *__pru_rproc_get(struct device_node *np, int index)
{
struct rproc *rproc;
phandle rproc_phandle;
int ret;
ret = of_property_read_u32_index(np, "ti,prus", index, &rproc_phandle);
if (ret)
return ERR_PTR(ret);
rproc = rproc_get_by_phandle(rproc_phandle);
if (!rproc) {
ret = -EPROBE_DEFER;
return ERR_PTR(ret);
}
/* make sure it is PRU rproc */
if (!is_pru_rproc(rproc->dev.parent)) {
rproc_put(rproc);
return ERR_PTR(-ENODEV);
}
return rproc;
}
/**
* pru_rproc_get() - get the PRU rproc instance from a device node
* @np: the user/client device node
* @index: index to use for the ti,prus property
* @pru_id: optional pointer to return the PRU remoteproc processor id
*
* This function looks through a client device node's "ti,prus" property at
* index @index and returns the rproc handle for a valid PRU remote processor if
* found. The function allows only one user to own the PRU rproc resource at a
* time. Caller must call pru_rproc_put() when done with using the rproc, not
* required if the function returns a failure.
*
* When optional @pru_id pointer is passed the PRU remoteproc processor id is
* returned.
*
* Return: rproc handle on success, and an ERR_PTR on failure using one
* of the following error values
* -ENODEV if device is not found
* -EBUSY if PRU is already acquired by anyone
* -EPROBE_DEFER is PRU device is not probed yet
*/
struct rproc *pru_rproc_get(struct device_node *np, int index,
enum pruss_pru_id *pru_id)
{
struct rproc *rproc;
struct pru_rproc *pru;
struct device *dev;
const char *fw_name;
int ret;
rproc = __pru_rproc_get(np, index);
if (IS_ERR(rproc))
return rproc;
pru = rproc->priv;
dev = &rproc->dev;
mutex_lock(&pru->lock);
if (pru->client_np) {
mutex_unlock(&pru->lock);
ret = -EBUSY;
goto err_no_rproc_handle;
}
pru->client_np = np;
rproc->sysfs_read_only = true;
mutex_unlock(&pru->lock);
if (pru_id)
*pru_id = pru->id;
ret = of_property_read_string_index(np, "firmware-name", index,
&fw_name);
if (!ret) {
ret = pru_rproc_set_firmware(rproc, fw_name);
if (ret) {
dev_err(dev, "failed to set firmware: %d\n", ret);
goto err;
}
}
return rproc;
err_no_rproc_handle:
rproc_put(rproc);
return ERR_PTR(ret);
err:
pru_rproc_put(rproc);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(pru_rproc_get);
/**
* pru_rproc_put() - release the PRU rproc resource
* @rproc: the rproc resource to release
*
* Releases the PRU rproc resource and makes it available to other
* users.
*/
void pru_rproc_put(struct rproc *rproc)
{
struct pru_rproc *pru;
if (IS_ERR_OR_NULL(rproc) || !is_pru_rproc(rproc->dev.parent))
return;
pru = rproc->priv;
pru_rproc_set_firmware(rproc, NULL);
mutex_lock(&pru->lock);
if (!pru->client_np) {
mutex_unlock(&pru->lock);
return;
}
pru->client_np = NULL;
rproc->sysfs_read_only = false;
mutex_unlock(&pru->lock);
rproc_put(rproc);
}
EXPORT_SYMBOL_GPL(pru_rproc_put);
/**
* pru_rproc_set_ctable() - set the constant table index for the PRU
* @rproc: the rproc instance of the PRU
* @c: constant table index to set
* @addr: physical address to set it to
*
* Return: 0 on success, or errno in error case.
*/
int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr)
{
struct pru_rproc *pru = rproc->priv;
unsigned int reg;
u32 mask, set;
u16 idx;
u16 idx_mask;
if (IS_ERR_OR_NULL(rproc))
return -EINVAL;
if (!rproc->dev.parent || !is_pru_rproc(rproc->dev.parent))
return -ENODEV;
/* pointer is 16 bit and index is 8-bit so mask out the rest */
idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF;
/* ctable uses bit 8 and upwards only */
idx = (addr >> 8) & idx_mask;
/* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */
reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1);
mask = idx_mask << (16 * (c & 1));
set = idx << (16 * (c & 1));
pru_control_set_reg(pru, reg, mask, set);
return 0;
}
EXPORT_SYMBOL_GPL(pru_rproc_set_ctable);
static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg)
{
return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg);
......@@ -438,7 +653,7 @@ static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len)
dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0];
dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1];
/* PRU1 has its local RAM addresses reversed */
if (pru->id == 1)
if (pru->id == PRUSS_PRU1)
swap(dram0, dram1);
shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2];
......@@ -747,14 +962,14 @@ static int pru_rproc_set_id(struct pru_rproc *pru)
case RTU0_IRAM_ADDR_MASK:
fallthrough;
case PRU0_IRAM_ADDR_MASK:
pru->id = 0;
pru->id = PRUSS_PRU0;
break;
case TX_PRU1_IRAM_ADDR_MASK:
fallthrough;
case RTU1_IRAM_ADDR_MASK:
fallthrough;
case PRU1_IRAM_ADDR_MASK:
pru->id = 1;
pru->id = PRUSS_PRU1;
break;
default:
ret = -EINVAL;
......@@ -816,6 +1031,9 @@ static int pru_rproc_probe(struct platform_device *pdev)
pru->pruss = platform_get_drvdata(ppdev);
pru->rproc = rproc;
pru->fw_name = fw_name;
pru->client_np = NULL;
spin_lock_init(&pru->rmw_lock);
mutex_init(&pru->lock);
for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
......@@ -904,7 +1122,7 @@ MODULE_DEVICE_TABLE(of, pru_rproc_match);
static struct platform_driver pru_rproc_driver = {
.driver = {
.name = "pru-rproc",
.name = PRU_RPROC_DRVNAME,
.of_match_table = pru_rproc_match,
.suppress_bind_attrs = true,
},
......@@ -916,5 +1134,7 @@ module_platform_driver(pru_rproc_driver);
MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
MODULE_AUTHOR("Puranjay Mohan <p-mohan@ti.com>");
MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>");
MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver");
MODULE_LICENSE("GPL v2");
drivers/remoteproc/qcom_common.c
View file @ f3a2439f
......@@ -101,7 +101,9 @@ static void qcom_minidump_cleanup(struct rproc *rproc)
}
}
static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsystem *subsystem)
static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsystem *subsystem,
void (*rproc_dumpfn_t)(struct rproc *rproc, struct rproc_dump_segment *segment,
void *dest, size_t offset, size_t size))
{
struct minidump_region __iomem *ptr;
struct minidump_region region;
......@@ -123,15 +125,15 @@ static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsy
for (i = 0; i < seg_cnt; i++) {
memcpy_fromio(&region, ptr + i, sizeof(region));
if (region.valid == MD_REGION_VALID) {
name = kstrdup(region.name, GFP_KERNEL);
if (le32_to_cpu(region.valid) == MD_REGION_VALID) {
name = kstrndup(region.name, MAX_REGION_NAME_LENGTH - 1, GFP_KERNEL);
if (!name) {
iounmap(ptr);
return -ENOMEM;
}
da = le64_to_cpu(region.address);
size = le32_to_cpu(region.size);
rproc_coredump_add_custom_segment(rproc, da, size, NULL, name);
size = le64_to_cpu(region.size);
rproc_coredump_add_custom_segment(rproc, da, size, rproc_dumpfn_t, name);
}
}
......@@ -139,7 +141,10 @@ static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsy
return 0;
}
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id)
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id,
void (*rproc_dumpfn_t)(struct rproc *rproc,
struct rproc_dump_segment *segment, void *dest, size_t offset,
size_t size))
{
int ret;
struct minidump_subsystem *subsystem;
......@@ -169,7 +174,7 @@ void qcom_minidump(struct rproc *rproc, unsigned int minidump_id)
return;
}
ret = qcom_add_minidump_segments(rproc, subsystem);
ret = qcom_add_minidump_segments(rproc, subsystem, rproc_dumpfn_t);
if (ret) {
dev_err(&rproc->dev, "Failed with error: %d while adding minidump entries\n", ret);
goto clean_minidump;
......
drivers/remoteproc/qcom_common.h
View file @ f3a2439f
......@@ -34,7 +34,10 @@ struct qcom_rproc_ssr {
struct qcom_ssr_subsystem *info;
};
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id);
void qcom_minidump(struct rproc *rproc, unsigned int minidump_id,
void (*rproc_dumpfn_t)(struct rproc *rproc,
struct rproc_dump_segment *segment, void *dest, size_t offset,
size_t size));
void qcom_add_glink_subdev(struct rproc *rproc, struct qcom_rproc_glink *glink,
const char *ssr_name);
......
drivers/remoteproc/qcom_q6v5.c
View file @ f3a2439f
......@@ -205,8 +205,8 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon)
q6v5->running = false;
/* Don't perform SMP2P dance if sysmon already shut down the remote */
if (qcom_sysmon_shutdown_acked(sysmon))
/* Don't perform SMP2P dance if remote isn't running */
if (q6v5->rproc->state != RPROC_RUNNING || qcom_sysmon_shutdown_acked(sysmon))
return 0;
qcom_smem_state_update_bits(q6v5->state,
......
drivers/remoteproc/qcom_q6v5_adsp.c
View file @ f3a2439f
......@@ -9,6 +9,7 @@
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iommu.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
......@@ -48,12 +49,18 @@
#define LPASS_PWR_ON_REG 0x10
#define LPASS_HALTREQ_REG 0x0
#define SID_MASK_DEFAULT 0xF
#define QDSP6SS_XO_CBCR 0x38
#define QDSP6SS_CORE_CBCR 0x20
#define QDSP6SS_SLEEP_CBCR 0x3c
#define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3
#define LPASS_BOOT_CORE_START BIT(0)
#define LPASS_BOOT_CMD_START BIT(0)
#define LPASS_EFUSE_Q6SS_EVB_SEL 0x0
struct adsp_pil_data {
int crash_reason_smem;
const char *firmware_name;
......@@ -62,6 +69,7 @@ struct adsp_pil_data {
const char *sysmon_name;
int ssctl_id;
bool is_wpss;
bool has_iommu;
bool auto_boot;
const char **clk_ids;
......@@ -82,6 +90,7 @@ struct qcom_adsp {
struct clk_bulk_data *clks;
void __iomem *qdsp6ss_base;
void __iomem *lpass_efuse;
struct reset_control *pdc_sync_reset;
struct reset_control *restart;
......@@ -99,6 +108,7 @@ struct qcom_adsp {
phys_addr_t mem_reloc;
void *mem_region;
size_t mem_size;
bool has_iommu;
struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX];
size_t proxy_pd_count;
......@@ -325,6 +335,48 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw)
return 0;
}
static void adsp_unmap_carveout(struct rproc *rproc)
{
struct qcom_adsp *adsp = rproc->priv;
if (adsp->has_iommu)
iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size);
}
static int adsp_map_carveout(struct rproc *rproc)
{
struct qcom_adsp *adsp = rproc->priv;
struct of_phandle_args args;
long long sid;
unsigned long iova;
int ret;
if (!adsp->has_iommu)
return 0;
if (!rproc->domain)
return -EINVAL;
ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);
if (ret < 0)
return ret;
sid = args.args[0] & SID_MASK_DEFAULT;
/* Add SID configuration for ADSP Firmware to SMMU */
iova = adsp->mem_phys | (sid << 32);
ret = iommu_map(rproc->domain, iova, adsp->mem_phys,
adsp->mem_size, IOMMU_READ | IOMMU_WRITE,
GFP_KERNEL);
if (ret) {
dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
return ret;
}
return 0;
}
static int adsp_start(struct rproc *rproc)
{
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
......@@ -335,9 +387,15 @@ static int adsp_start(struct rproc *rproc)
if (ret)
return ret;
ret = adsp_map_carveout(rproc);
if (ret) {
dev_err(adsp->dev, "ADSP smmu mapping failed\n");
goto disable_irqs;
}
ret = clk_prepare_enable(adsp->xo);
if (ret)
goto disable_irqs;
goto adsp_smmu_unmap;
ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds,
adsp->proxy_pd_count);
......@@ -362,11 +420,14 @@ static int adsp_start(struct rproc *rproc)
/* Program boot address */
writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
if (adsp->lpass_efuse)
writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
/* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
writel(0x1, adsp->qdsp6ss_base + CORE_START_REG);
writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
/* Trigger boot FSM to start QDSP6 */
writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG);
writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
/* Wait for core to come out of reset */
ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
......@@ -390,6 +451,8 @@ static int adsp_start(struct rproc *rproc)
qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
disable_xo_clk:
clk_disable_unprepare(adsp->xo);
adsp_smmu_unmap:
adsp_unmap_carveout(rproc);
disable_irqs:
qcom_q6v5_unprepare(&adsp->q6v5);
......@@ -418,6 +481,8 @@ static int adsp_stop(struct rproc *rproc)
if (ret)
dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
adsp_unmap_carveout(rproc);
handover = qcom_q6v5_unprepare(&adsp->q6v5);
if (handover)
qcom_adsp_pil_handover(&adsp->q6v5);
......@@ -437,6 +502,27 @@ static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iom
return adsp->mem_region + offset;
}
static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw)
{
struct qcom_adsp *adsp = rproc->priv;
int ret;
ret = qcom_register_dump_segments(rproc, fw);
if (ret) {
dev_err(&rproc->dev, "Error in registering dump segments\n");
return ret;
}
if (adsp->has_iommu) {
ret = rproc_elf_load_rsc_table(rproc, fw);
if (ret) {
dev_err(&rproc->dev, "Error in loading resource table\n");
return ret;
}
}
return 0;
}
static unsigned long adsp_panic(struct rproc *rproc)
{
struct qcom_adsp *adsp = rproc->priv;
......@@ -448,7 +534,7 @@ static const struct rproc_ops adsp_ops = {
.start = adsp_start,
.stop = adsp_stop,
.da_to_va = adsp_da_to_va,
.parse_fw = qcom_register_dump_segments,
.parse_fw = adsp_parse_firmware,
.load = adsp_load,
.panic = adsp_panic,
};
......@@ -507,6 +593,7 @@ static int adsp_init_reset(struct qcom_adsp *adsp)
static int adsp_init_mmio(struct qcom_adsp *adsp,
struct platform_device *pdev)
{
struct resource *efuse_region;
struct device_node *syscon;
int ret;
......@@ -516,6 +603,17 @@ static int adsp_init_mmio(struct qcom_adsp *adsp,
return PTR_ERR(adsp->qdsp6ss_base);
}
efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!efuse_region) {
adsp->lpass_efuse = NULL;
dev_dbg(adsp->dev, "failed to get efuse memory region\n");
} else {
adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);
if (IS_ERR(adsp->lpass_efuse)) {
dev_err(adsp->dev, "failed to map efuse registers\n");
return PTR_ERR(adsp->lpass_efuse);
}
}
syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
if (!syscon) {
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
......@@ -595,12 +693,15 @@ static int adsp_probe(struct platform_device *pdev)
}
rproc->auto_boot = desc->auto_boot;
rproc->has_iommu = desc->has_iommu;
rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
adsp = (struct qcom_adsp *)rproc->priv;
adsp->dev = &pdev->dev;
adsp->rproc = rproc;
adsp->info_name = desc->sysmon_name;
adsp->has_iommu = desc->has_iommu;
platform_set_drvdata(pdev, adsp);
if (desc->is_wpss)
......@@ -696,6 +797,21 @@ static const struct adsp_pil_data adsp_resource_init = {
},
};
static const struct adsp_pil_data adsp_sc7280_resource_init = {
.crash_reason_smem = 423,
.firmware_name = "adsp.pbn",
.load_state = "adsp",
.ssr_name = "lpass",
.sysmon_name = "adsp",
.ssctl_id = 0x14,
.has_iommu = true,
.auto_boot = true,
.clk_ids = (const char*[]) {
"gcc_cfg_noc_lpass", NULL
},
.num_clks = 1,
};
static const struct adsp_pil_data cdsp_resource_init = {
.crash_reason_smem = 601,
.firmware_name = "cdsp.mdt",
......@@ -734,6 +850,7 @@ static const struct adsp_pil_data wpss_resource_init = {
static const struct of_device_id adsp_of_match[] = {
{ .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
{ .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
{ .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },
{ .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
{ },
......
drivers/remoteproc/qcom_q6v5_mss.c
View file @ f3a2439f
This diff is collapsed.
drivers/remoteproc/qcom_q6v5_pas.c
View file @ f3a2439f
This diff is collapsed.
drivers/remoteproc/qcom_sysmon.c
View file @ f3a2439f
......@@ -388,7 +388,7 @@ static void ssctl_send_event(struct qcom_sysmon *sysmon,
}
memset(&req, 0, sizeof(req));
strlcpy(req.subsys_name, event->subsys_name, sizeof(req.subsys_name));
strscpy(req.subsys_name, event->subsys_name, sizeof(req.subsys_name));
req.subsys_name_len = strlen(req.subsys_name);
req.event = event->ssr_event;
req.evt_driven_valid = true;
......
drivers/remoteproc/qcom_wcnss.c
View file @ f3a2439f
......@@ -141,6 +141,17 @@ static const struct wcnss_data pronto_v2_data = {
.num_vregs = 1,
};
static const struct wcnss_data pronto_v3_data = {
.pmu_offset = 0x1004,
.spare_offset = 0x1088,
.pd_names = { "mx", "cx" },
.vregs = (struct wcnss_vreg_info[]) {
{ "vddpx", 1800000, 1800000, 0 },
},
.num_vregs = 1,
};
static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
{
struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
......@@ -675,6 +686,7 @@ static const struct of_device_id wcnss_of_match[] = {
{ .compatible = "qcom,riva-pil", &riva_data },
{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
{ .compatible = "qcom,pronto-v3-pil", &pronto_v3_data },
{ },
};
MODULE_DEVICE_TABLE(of, wcnss_of_match);
......
drivers/remoteproc/qcom_wcnss.h
View file @ f3a2439f
......@@ -5,8 +5,6 @@
struct qcom_iris;
struct qcom_wcnss;
extern struct platform_driver qcom_iris_driver;
struct wcnss_vreg_info {
const char * const name;
int min_voltage;
......
drivers/remoteproc/ti_k3_dsp_remoteproc.c
View file @ f3a2439f
......@@ -870,6 +870,10 @@ static const struct k3_dsp_mem_data c71_mems[] = {
{ .name = "l1dram", .dev_addr = 0xe00000 },
};
static const struct k3_dsp_mem_data c7xv_mems[] = {
{ .name = "l2sram", .dev_addr = 0x800000 },
};
static const struct k3_dsp_dev_data c66_data = {
.mems = c66_mems,
.num_mems = ARRAY_SIZE(c66_mems),
......@@ -884,10 +888,18 @@ static const struct k3_dsp_dev_data c71_data = {
.uses_lreset = false,
};
static const struct k3_dsp_dev_data c7xv_data = {
.mems = c7xv_mems,
.num_mems = ARRAY_SIZE(c7xv_mems),
.boot_align_addr = SZ_2M,
.uses_lreset = false,
};
static const struct of_device_id k3_dsp_of_match[] = {
{ .compatible = "ti,j721e-c66-dsp", .data = &c66_data, },
{ .compatible = "ti,j721e-c71-dsp", .data = &c71_data, },
{ .compatible = "ti,j721s2-c71-dsp", .data = &c71_data, },
{ .compatible = "ti,am62a-c7xv-dsp", .data = &c7xv_data, },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, k3_dsp_of_match);
......
include/linux/remoteproc/pruss.h 0 → 100644
View file @ f3a2439f
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* PRU-ICSS Subsystem user interfaces
*
* Copyright (C) 2015-2022 Texas Instruments Incorporated - http://www.ti.com
* Suman Anna <s-anna@ti.com>
*/
#ifndef __LINUX_PRUSS_H
#define __LINUX_PRUSS_H
#include <linux/device.h>
#include <linux/types.h>
#define PRU_RPROC_DRVNAME "pru-rproc"
/**
* enum pruss_pru_id - PRU core identifiers
* @PRUSS_PRU0: PRU Core 0.
* @PRUSS_PRU1: PRU Core 1.
* @PRUSS_NUM_PRUS: Total number of PRU Cores available.
*
*/
enum pruss_pru_id {
PRUSS_PRU0 = 0,
PRUSS_PRU1,
PRUSS_NUM_PRUS,
};
/*
* enum pru_ctable_idx - Configurable Constant table index identifiers
*/
enum pru_ctable_idx {
PRU_C24 = 0,
PRU_C25,
PRU_C26,
PRU_C27,
PRU_C28,
PRU_C29,
PRU_C30,
PRU_C31,
};
struct device_node;
struct rproc;
#if IS_ENABLED(CONFIG_PRU_REMOTEPROC)
struct rproc *pru_rproc_get(struct device_node *np, int index,
enum pruss_pru_id *pru_id);
void pru_rproc_put(struct rproc *rproc);
int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr);
#else
static inline struct rproc *
pru_rproc_get(struct device_node *np, int index, enum pruss_pru_id *pru_id)
{
return ERR_PTR(-EOPNOTSUPP);
}
static inline void pru_rproc_put(struct rproc *rproc) { }
static inline int pru_rproc_set_ctable(struct rproc *rproc,
enum pru_ctable_idx c, u32 addr)
{
return -EOPNOTSUPP;
}
#endif /* CONFIG_PRU_REMOTEPROC */
static inline bool is_pru_rproc(struct device *dev)
{
const char *drv_name = dev_driver_string(dev);
if (strncmp(drv_name, PRU_RPROC_DRVNAME, sizeof(PRU_RPROC_DRVNAME)))
return false;
return true;
}
#endif /* __LINUX_PRUSS_H */
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