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Commit f3a4d7c3 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'qcom-arm64-for-6.8-2' of... 

Merge tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

A few more Qualcomm Arm64 DeviceTree updates for v6.8

This corrects the rate of the UTMI clock on IPQ6018 USB0. The SDHCI
controller on SC7280 gains missing markings for being cache-coherent.
For SC8180X a typo in assignment of PCIe refgen clocks is corrected, PCI
controllers are marked cache-coherent, and the USB SS PHY interrupts are
corrected to allow wakeup.

Similarly USB HS PHY and SS PHY interrupts are corrected to allow
wakeup on SDM670.

On SM8550 the X3 cluster idle state is properly described, and the
latency numbers are adjusted for all the idle states.

The PM8550 regulator supplies on X1E are corrected to match the driver
and binding, and the timer node is updated to avoid an unnecessary
validation error.

* tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: dts: qcom: sc8180x: Fix up PCIe nodes
  arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent
  arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550
  arm64: dts: qcom: sm8550: Update idle state time requirements
  arm64: dts: qcom: sm8550: Separate out X3 idle state
  arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK
  arm64: dts: qcom: x1e80100: align mem timer size cells with bindings
  arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent
  arm64: dts: qcom: sc8180x: fix USB SS wakeup
  arm64: dts: qcom: sdm670: fix USB SS wakeup
  arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts

Link: https://lore.kernel.org/r/20231231034108.3262678-1-andersson@kernel.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 2f5ed2ca 78403b37
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Showing with 48 additions and 34 deletions
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file @ f3a4d7c3
......@@ -628,7 +628,7 @@ usb3: usb@8af8800 {
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
<20000000>;
<24000000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
......
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ f3a4d7c3
......@@ -1000,6 +1000,7 @@ sdhc_1: mmc@7c4000 {
bus-width = <8>;
supports-cqe;
dma-coherent;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
......@@ -3458,6 +3459,7 @@ sdhc_2: mmc@8804000 {
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
dma-coherent;
qcom,dll-config = <0x0007642c>;
......
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View file @ f3a4d7c3
......@@ -1751,6 +1751,7 @@ pcie0: pcie@1c00000 {
phys = <&pcie0_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -1761,7 +1762,7 @@ pcie0_phy: phy@1c06000 {
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
......@@ -1847,6 +1848,7 @@ pcie3: pcie@1c08000 {
phys = <&pcie3_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -1857,7 +1859,7 @@ pcie3_phy: phy@1c0c000 {
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3_CLKREF_CLK>,
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_3_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
......@@ -1944,6 +1946,7 @@ pcie1: pcie@1c10000 {
phys = <&pcie1_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -2041,6 +2044,7 @@ pcie2: pcie@1c18000 {
phys = <&pcie2_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -2059,7 +2063,7 @@ pcie2_phy: phy@1c1c000 {
"refgen",
"pipe";
#clock-cells = <0>;
clock-output-names = "pcie_3_pipe_clk";
clock-output-names = "pcie_2_pipe_clk";
#phy-cells = <0>;
......@@ -2554,7 +2558,7 @@ usb_prim: usb@a6f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
......@@ -2628,7 +2632,7 @@ usb_sec: usb@a8f8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
......
arch/arm64/boot/dts/qcom/sdm670.dtsi
View file @ f3a4d7c3
......@@ -1320,10 +1320,10 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
......
arch/arm64/boot/dts/qcom/sm8550.dtsi
View file @ f3a4d7c3
......@@ -285,9 +285,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <800>;
entry-latency-us = <550>;
exit-latency-us = <750>;
min-residency-us = <4090>;
min-residency-us = <6700>;
local-timer-stop;
};
......@@ -296,8 +296,18 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <600>;
exit-latency-us = <1550>;
min-residency-us = <4791>;
exit-latency-us = <1300>;
min-residency-us = <8136>;
local-timer-stop;
};
PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
idle-state-name = "goldplus-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <500>;
exit-latency-us = <1350>;
min-residency-us = <7480>;
local-timer-stop;
};
};
......@@ -306,17 +316,17 @@ domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <1050>;
exit-latency-us = <2500>;
min-residency-us = <5309>;
entry-latency-us = <750>;
exit-latency-us = <2350>;
min-residency-us = <9144>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2700>;
exit-latency-us = <3500>;
min-residency-us = <13959>;
entry-latency-us = <2800>;
exit-latency-us = <4400>;
min-residency-us = <10150>;
};
};
};
......@@ -401,7 +411,7 @@ CPU_PD6: power-domain-cpu6 {
CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
domain-idle-states = <&PRIME_CPU_SLEEP_0>;
};
CLUSTER_PD: power-domain-cluster {
......
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
View file @ f3a4d7c3
......@@ -40,13 +40,11 @@ regulators-0 {
vdd-bob1-supply = <&vph_pwr>;
vdd-bob2-supply = <&vph_pwr>;
vdd-l1-supply = <&vreg_s4c_1p8>;
vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
vdd-l2-l13-l14-supply = <&vreg_bob1>;
vdd-l4-supply = <&vreg_s4c_1p8>;
vdd-l5-l16-supply = <&vreg_bob1>;
vdd-l6-l7-supply = <&vreg_bob2>;
vdd-l8-l9-supply = <&vreg_bob1>;
vdd-l10-supply = <&vreg_s4c_1p8>;
vdd-l12-supply = <&vreg_s5j_1p2>;
vdd-l15-supply = <&vreg_s4c_1p8>;
vdd-l17-supply = <&vreg_bob2>;
......
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View file @ f3a4d7c3
......@@ -3418,12 +3418,12 @@ timer@17800000 {
reg = <0 0x17800000 0 0x1000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
#size-cells = <1>;
ranges = <0 0 0 0 0x20000000>;
frame@17801000 {
reg = <0 0x17801000 0 0x1000>,
<0 0x17802000 0 0x1000>;
reg = <0 0x17801000 0x1000>,
<0 0x17802000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3432,7 +3432,7 @@ frame@17801000 {
};
frame@17803000 {
reg = <0 0x17803000 0 0x1000>;
reg = <0 0x17803000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3442,7 +3442,7 @@ frame@17803000 {
};
frame@17805000 {
reg = <0 0x17805000 0 0x1000>;
reg = <0 0x17805000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3452,7 +3452,7 @@ frame@17805000 {
};
frame@17807000 {
reg = <0 0x17807000 0 0x1000>;
reg = <0 0x17807000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3462,7 +3462,7 @@ frame@17807000 {
};
frame@17809000 {
reg = <0 0x17809000 0 0x1000>;
reg = <0 0x17809000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3472,7 +3472,7 @@ frame@17809000 {
};
frame@1780b000 {
reg = <0 0x1780b000 0 0x1000>;
reg = <0 0x1780b000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
......@@ -3482,7 +3482,7 @@ frame@1780b000 {
};
frame@1780d000 {
reg = <0 0x1780d000 0 0x1000>;
reg = <0 0x1780d000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
......
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