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Commit f3eda8f5 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
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Merge branch 'perf/uncore-json-updates-1' of... 

Merge branch 'perf/uncore-json-updates-1' of git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux-misc into perf/core

Pull perf/core improvements from Andi Kleen:

This pull requests contains updates to the Intel PMU events JSON files,
plus two one liner code fixes for the JSON files (also appended as patch)

The most remarkable change is support for Sandy Bridge to Skylake
client uncore event list support.
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parents f5a70801 3401e8d1
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Showing with 1546 additions and 3 deletions
tools/perf/pmu-events/arch/x86/broadwell/uncore.json 0 → 100644
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tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
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......@@ -19,12 +19,19 @@
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "Memory controller clock ticks",
"Counter": "0,1,2,3",
"EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_DCLOCKTICKS) * 100.",
"MetricName": "power_channel_ppd %",
"PerPkg": "1",
"Unit": "iMC"
......@@ -34,7 +41,7 @@
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.",
"MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_DCLOCKTICKS) * 100.",
"MetricName": "power_critical_throttle_cycles %",
"PerPkg": "1",
"Unit": "iMC"
......@@ -44,7 +51,7 @@
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_DCLOCKTICKS) * 100.",
"MetricName": "power_self_refresh %",
"PerPkg": "1",
"Unit": "iMC"
......
tools/perf/pmu-events/arch/x86/haswell/uncore.json 0 → 100644
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tools/perf/pmu-events/arch/x86/ivybridge/uncore.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sandybridge/uncore.json 0 → 100644
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tools/perf/pmu-events/arch/x86/skylake/uncore.json 0 → 100644
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[
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x41",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x81",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x44",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x48",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x21",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x81",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x18",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x88",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x1f",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x2f",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x8f",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x86",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x16",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "CBO",
"EventCode": "0x34",
"UMask": "0x26",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"Counter": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x81",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x81",
"UMask": "0x02",
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x81",
"UMask": "0x20",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x84",
"UMask": "0x01",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "iMPH-U",
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"Counter": "0",
"CounterMask": "1",
"Invert": "0",
"EdgeDetect": "0"
},
{
"Unit": "NCU",
"EventCode": "0x0",
"UMask": "0x01",
"EventName": "UNC_CLOCK.SOCKET",
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"Counter": "FIXED",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
}
]
\ No newline at end of file
tools/perf/pmu-events/jevents.c
View file @ f3eda8f5
......@@ -195,6 +195,7 @@ static struct map {
{ "CBO", "uncore_cbox" },
{ "QPI LL", "uncore_qpi" },
{ "SBO", "uncore_sbox" },
{ "iMPH-U", "uncore_arb" },
{}
};
......@@ -468,6 +469,7 @@ int json_events(const char *fn,
}
addfield(map, &desc, ". ", "Unit: ", NULL);
addfield(map, &desc, "", pmu, NULL);
addfield(map, &desc, "", " ", NULL);
} else if (json_streq(map, field, "Filter")) {
addfield(map, &filter, "", "", val);
} else if (json_streq(map, field, "ScaleUnit")) {
......
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