Commit f5c2f9f9 authored by Brad Larson's avatar Brad Larson Committed by Mark Brown

spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC

The AMD Pensando Elba SoC has the Cadence QSPI controller integrated.

The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled
a dummy readback from the controller is performed to ensure
synchronization.

Signed-off-by: Brad Larson <blarson@amd.com
Link: https://lore.kernel.org/r/20230515181606.65953-8-blarson@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org
parent 9f34baf6
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
#define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_SLOW_SRAM BIT(4)
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
/* Capabilities */ /* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0) #define CQSPI_SUPPORTS_OCTAL BIT(0)
...@@ -90,6 +91,7 @@ struct cqspi_st { ...@@ -90,6 +91,7 @@ struct cqspi_st {
u32 pd_dev_id; u32 pd_dev_id;
bool wr_completion; bool wr_completion;
bool slow_sram; bool slow_sram;
bool apb_ahb_hazard;
}; };
struct cqspi_driver_platdata { struct cqspi_driver_platdata {
...@@ -1027,6 +1029,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, ...@@ -1027,6 +1029,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
if (cqspi->wr_delay) if (cqspi->wr_delay)
ndelay(cqspi->wr_delay); ndelay(cqspi->wr_delay);
/*
* If a hazard exists between the APB and AHB interfaces, perform a
* dummy readback from the controller to ensure synchronization.
*/
if (cqspi->apb_ahb_hazard)
readl(reg_base + CQSPI_REG_INDIRECTWR);
while (remaining > 0) { while (remaining > 0) {
size_t write_words, mod_bytes; size_t write_words, mod_bytes;
...@@ -1754,6 +1763,8 @@ static int cqspi_probe(struct platform_device *pdev) ...@@ -1754,6 +1763,8 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->wr_completion = false; cqspi->wr_completion = false;
if (ddata->quirks & CQSPI_SLOW_SRAM) if (ddata->quirks & CQSPI_SLOW_SRAM)
cqspi->slow_sram = true; cqspi->slow_sram = true;
if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR)
cqspi->apb_ahb_hazard = true;
if (of_device_is_compatible(pdev->dev.of_node, if (of_device_is_compatible(pdev->dev.of_node,
"xlnx,versal-ospi-1.0")) "xlnx,versal-ospi-1.0"))
...@@ -1885,6 +1896,10 @@ static const struct cqspi_driver_platdata jh7110_qspi = { ...@@ -1885,6 +1896,10 @@ static const struct cqspi_driver_platdata jh7110_qspi = {
.quirks = CQSPI_DISABLE_DAC_MODE, .quirks = CQSPI_DISABLE_DAC_MODE,
}; };
static const struct cqspi_driver_platdata pensando_cdns_qspi = {
.quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
};
static const struct of_device_id cqspi_dt_ids[] = { static const struct of_device_id cqspi_dt_ids[] = {
{ {
.compatible = "cdns,qspi-nor", .compatible = "cdns,qspi-nor",
...@@ -1914,6 +1929,10 @@ static const struct of_device_id cqspi_dt_ids[] = { ...@@ -1914,6 +1929,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "starfive,jh7110-qspi", .compatible = "starfive,jh7110-qspi",
.data = &jh7110_qspi, .data = &jh7110_qspi,
}, },
{
.compatible = "amd,pensando-elba-qspi",
.data = &pensando_cdns_qspi,
},
{ /* end of table */ } { /* end of table */ }
}; };
......
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