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Commit f5ef85ad authored by Johan Hovold's avatar Johan Hovold Committed by Vinod Koul
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phy: qcom-qmp-usb: clean up status polling 

Clean up the PHY status polling by dropping the configuration mask which
is no longer needed since the QMP driver split.
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-13-johan+linaro@kernel.orgSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 7516edbf
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Showing with 2 additions and 23 deletions
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
View file @ f5ef85ad
...@@ -1445,8 +1445,6 @@ struct qmp_phy_cfg { ...@@ -1445,8 +1445,6 @@ struct qmp_phy_cfg {
unsigned int start_ctrl; unsigned int start_ctrl;
unsigned int pwrdn_ctrl; unsigned int pwrdn_ctrl;
/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
unsigned int phy_status;
/* true, if PHY needs delay after POWER_DOWN */ /* true, if PHY needs delay after POWER_DOWN */
bool has_pwrdn_delay; bool has_pwrdn_delay;
...@@ -1604,7 +1602,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { ...@@ -1604,7 +1602,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
}; };
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
...@@ -1628,7 +1625,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ...@@ -1628,7 +1625,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
}; };
static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
...@@ -1652,7 +1648,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ...@@ -1652,7 +1648,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.has_phy_dp_com_ctrl = true, .has_phy_dp_com_ctrl = true,
...@@ -1679,7 +1674,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { ...@@ -1679,7 +1674,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.has_phy_dp_com_ctrl = true, .has_phy_dp_com_ctrl = true,
...@@ -1706,7 +1700,6 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { ...@@ -1706,7 +1700,6 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
}; };
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
...@@ -1730,7 +1723,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ...@@ -1730,7 +1723,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
}; };
...@@ -1756,7 +1748,6 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ...@@ -1756,7 +1748,6 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
}; };
static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
...@@ -1783,7 +1774,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ...@@ -1783,7 +1774,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.has_phy_dp_com_ctrl = true, .has_phy_dp_com_ctrl = true,
...@@ -1813,7 +1803,6 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { ...@@ -1813,7 +1803,6 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
}; };
...@@ -1842,7 +1831,6 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ...@@ -1842,7 +1831,6 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.has_phy_dp_com_ctrl = true, .has_phy_dp_com_ctrl = true,
...@@ -1872,7 +1860,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { ...@@ -1872,7 +1860,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
}; };
...@@ -1901,7 +1888,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ...@@ -1901,7 +1888,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
}; };
...@@ -1930,7 +1916,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ...@@ -1930,7 +1916,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
}; };
...@@ -1959,7 +1944,6 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ...@@ -1959,7 +1944,6 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
.has_phy_dp_com_ctrl = true, .has_phy_dp_com_ctrl = true,
...@@ -1989,7 +1973,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { ...@@ -1989,7 +1973,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
.has_pwrdn_delay = true, .has_pwrdn_delay = true,
}; };
...@@ -2015,7 +1998,6 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ...@@ -2015,7 +1998,6 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
.start_ctrl = SERDES_START | PCS_START, .start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN, .pwrdn_ctrl = SW_PWRDN,
.phy_status = PHYSTATUS,
}; };
static void qmp_usb_configure_lane(void __iomem *base, static void qmp_usb_configure_lane(void __iomem *base,
...@@ -2147,7 +2129,7 @@ static int qmp_usb_power_on(struct phy *phy) ...@@ -2147,7 +2129,7 @@ static int qmp_usb_power_on(struct phy *phy)
void __iomem *rx = qphy->rx; void __iomem *rx = qphy->rx;
void __iomem *pcs = qphy->pcs; void __iomem *pcs = qphy->pcs;
void __iomem *status; void __iomem *status;
unsigned int mask, val, ready; unsigned int val;
int ret; int ret;
qmp_usb_serdes_init(qphy); qmp_usb_serdes_init(qphy);
...@@ -2181,10 +2163,7 @@ static int qmp_usb_power_on(struct phy *phy) ...@@ -2181,10 +2163,7 @@ static int qmp_usb_power_on(struct phy *phy)
qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
status = pcs + cfg->regs[QPHY_PCS_STATUS]; status = pcs + cfg->regs[QPHY_PCS_STATUS];
mask = cfg->phy_status; ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 10,
ready = 0;
ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
PHY_INIT_COMPLETE_TIMEOUT); PHY_INIT_COMPLETE_TIMEOUT);
if (ret) { if (ret) {
dev_err(qmp->dev, "phy initialization timed-out\n"); dev_err(qmp->dev, "phy initialization timed-out\n");
......
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