Commit f6317573 authored by Kousik Sanagavarapu's avatar Kousik Sanagavarapu Committed by Mark Brown

spi: dt-bindings: armada-3700: convert to dtschema

Convert txt binding of marvell armada 3700 SoC spi controller to dtschema
to allow for validation.
Signed-off-by: default avatarKousik Sanagavarapu <five231003@gmail.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240417052729.6612-1-five231003@gmail.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4fbf4e3e
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/marvell,armada-3700-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 3700 SPI Controller
description:
The SPI controller on Marvell Armada 3700 SoC.
maintainers:
- Kousik Sanagavarapu <five231003@gmail.com>
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
const: marvell,armada-3700-spi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
num-cs:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10600 0x5d>;
clocks = <&nb_perih_clk 7>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <4>;
};
...
* Marvell Armada 3700 SPI Controller
Required Properties:
- compatible: should be "marvell,armada-3700-spi"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The interrupt number. The interrupt specifier format depends on
the interrupt controller and of its driver.
- clocks: Must contain the clock source, usually from the North Bridge clocks.
- num-cs: The number of chip selects that is supported by this SPI Controller
- #address-cells: should be 1.
- #size-cells: should be 0.
Example:
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10600 0x5d>;
clocks = <&nb_perih_clk 7>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <4>;
};
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