Commit f74d2182 authored by Mark Brown's avatar Mark Brown

spi: spi-zyqnmp-gqspi: Add tap delay and Versal platform support

Merge series from Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>:

A bunch of improvements to the driver:

- Fix kernel-doc warnings in GQSPI driver.
- Avoid setting CPOL, CPHA & baud rate multiple times.
- Add Versal platform support in GQSPI driver.
- Add tap delay support in GQSPI driver.
parents a977c3a9 29f4d95b
...@@ -14,7 +14,9 @@ allOf: ...@@ -14,7 +14,9 @@ allOf:
properties: properties:
compatible: compatible:
const: xlnx,zynqmp-qspi-1.0 enum:
- xlnx,versal-qspi-1.0
- xlnx,zynqmp-qspi-1.0
reg: reg:
maxItems: 2 maxItems: 2
......
...@@ -843,6 +843,13 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value) ...@@ -843,6 +843,13 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
} }
EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs); EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
{
return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,
index, value, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);
/** /**
* zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
* @value: Status value to be written * @value: Status value to be written
......
This diff is collapsed.
...@@ -135,6 +135,7 @@ enum pm_ret_status { ...@@ -135,6 +135,7 @@ enum pm_ret_status {
}; };
enum pm_ioctl_id { enum pm_ioctl_id {
IOCTL_SET_TAPDELAY_BYPASS = 4,
IOCTL_SD_DLL_RESET = 6, IOCTL_SD_DLL_RESET = 6,
IOCTL_SET_SD_TAPDELAY = 7, IOCTL_SET_SD_TAPDELAY = 7,
IOCTL_SET_PLL_FRAC_MODE = 8, IOCTL_SET_PLL_FRAC_MODE = 8,
...@@ -389,6 +390,18 @@ enum zynqmp_pm_shutdown_subtype { ...@@ -389,6 +390,18 @@ enum zynqmp_pm_shutdown_subtype {
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
}; };
enum tap_delay_signal_type {
PM_TAPDELAY_NAND_DQS_IN = 0,
PM_TAPDELAY_NAND_DQS_OUT = 1,
PM_TAPDELAY_QSPI = 2,
PM_TAPDELAY_MAX = 3,
};
enum tap_delay_bypass_ctrl {
PM_TAPDELAY_BYPASS_DISABLE = 0,
PM_TAPDELAY_BYPASS_ENABLE = 1,
};
enum ospi_mux_select_type { enum ospi_mux_select_type {
PM_OSPI_MUX_SEL_DMA = 0, PM_OSPI_MUX_SEL_DMA = 0,
PM_OSPI_MUX_SEL_LINEAR = 1, PM_OSPI_MUX_SEL_LINEAR = 1,
...@@ -484,6 +497,7 @@ int zynqmp_pm_write_ggs(u32 index, u32 value); ...@@ -484,6 +497,7 @@ int zynqmp_pm_write_ggs(u32 index, u32 value);
int zynqmp_pm_read_ggs(u32 index, u32 *value); int zynqmp_pm_read_ggs(u32 index, u32 *value);
int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value); int zynqmp_pm_set_boot_health_status(u32 value);
int zynqmp_pm_pinctrl_request(const u32 pin); int zynqmp_pm_pinctrl_request(const u32 pin);
...@@ -696,6 +710,11 @@ static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) ...@@ -696,6 +710,11 @@ static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
return -ENODEV; return -ENODEV;
} }
static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
{
return -ENODEV;
}
static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
{ {
return -ENODEV; return -ENODEV;
......
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