Commit f793e454 authored by Jonathan Marek's avatar Jonathan Marek Committed by Stephen Boyd

dt-bindings: clock: add SM8150 QCOM Graphics clock bindings

Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8150 SoCs.
Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Tested-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-8-jonathan@marek.caReviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 23e2653e
...@@ -11,17 +11,19 @@ maintainers: ...@@ -11,17 +11,19 @@ maintainers:
description: | description: |
Qualcomm graphics clock control module which supports the clocks, resets and Qualcomm graphics clock control module which supports the clocks, resets and
power domains on SDM845/SC7180. power domains on SDM845/SC7180/SM8150.
See also: See also:
dt-bindings/clock/qcom,gpucc-sdm845.h dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sm8150.h
properties: properties:
compatible: compatible:
enum: enum:
- qcom,sdm845-gpucc - qcom,sdm845-gpucc
- qcom,sc7180-gpucc - qcom,sc7180-gpucc
- qcom,sm8150-gpucc
clocks: clocks:
items: items:
......
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
/* GPU_CC clock registers */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CRC_AHB_CLK 1
#define GPU_CC_CX_APB_CLK 2
#define GPU_CC_CX_GMU_CLK 3
#define GPU_CC_CX_SNOC_DVM_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_GMU_CLK_SRC 7
#define GPU_CC_GX_GMU_CLK 8
#define GPU_CC_PLL1 9
/* GPU_CC Resets */
#define GPUCC_GPU_CC_CX_BCR 0
#define GPUCC_GPU_CC_GFX3D_AON_BCR 1
#define GPUCC_GPU_CC_GMU_BCR 2
#define GPUCC_GPU_CC_GX_BCR 3
#define GPUCC_GPU_CC_SPDM_BCR 4
#define GPUCC_GPU_CC_XO_BCR 5
/* GPU_CC GDSCRs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif
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