Commit f8386b35 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu: add new flag AMD_PG_SUPPORT_MMHUB

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a95890b4
...@@ -698,6 +698,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) ...@@ -698,6 +698,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
mmhub_v1_0_initialize_power_gating(adev); mmhub_v1_0_initialize_power_gating(adev);
mmhub_v1_0_update_power_gating(adev, true);
break; break;
default: default:
break; break;
......
...@@ -426,7 +426,7 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, ...@@ -426,7 +426,7 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
if (enable) { if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
PCTL0_RENG_EXECUTE, PCTL0_RENG_EXECUTE,
RENG_EXECUTE_ON_PWR_UP, 1); RENG_EXECUTE_ON_PWR_UP, 1);
......
...@@ -184,6 +184,7 @@ enum amd_fan_ctrl_mode { ...@@ -184,6 +184,7 @@ enum amd_fan_ctrl_mode {
#define AMD_PG_SUPPORT_SAMU (1 << 10) #define AMD_PG_SUPPORT_SAMU (1 << 10)
#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
#define AMD_PG_SUPPORT_MMHUB (1 << 13)
enum amd_pm_state_type { enum amd_pm_state_type {
/* not used for dpm */ /* not used for dpm */
......
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