Commit f95f57e4 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Andy Gross

arm64: dts: qcom: qcs404: Fix regulator supply names

The regulator definition got their supply names cleaned up during
upstreaming, so they no longer match the driver defined names. Update
the supply names.

Also fill out the missing voltage of SMPS 5.

Fixes: 0b363f5b ("arm64: dts: qcom: qcs404: Add PMS405 RPM regulators")
Reported-by: default avatarNicolas Dechesne <nicolas.dechesne@linaro.org>
Reviewed-by: default avatarNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent d6e5a4f8
...@@ -37,18 +37,18 @@ &rpm_requests { ...@@ -37,18 +37,18 @@ &rpm_requests {
pms405-regulators { pms405-regulators {
compatible = "qcom,rpm-pms405-regulators"; compatible = "qcom,rpm-pms405-regulators";
vdd-s1-supply = <&vph_pwr>; vdd_s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>; vdd_s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>; vdd_s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>; vdd_s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>; vdd_s5-supply = <&vph_pwr>;
vdd-l1-l2-supply = <&vreg_s5_1p35>; vdd_l1_l2-supply = <&vreg_s5_1p35>;
vdd-l3-l8-supply = <&vreg_s5_1p35>; vdd_l3_l8-supply = <&vreg_s5_1p35>;
vdd-l4-supply = <&vreg_s5_1p35>; vdd_l4-supply = <&vreg_s5_1p35>;
vdd-l5-l6-supply = <&vreg_s4_1p8>; vdd_l5_l6-supply = <&vreg_s4_1p8>;
vdd-l7-supply = <&vph_pwr>; vdd_l7-supply = <&vph_pwr>;
vdd-l9-supply = <&vreg_s5_1p35>; vdd_l9-supply = <&vreg_s5_1p35>;
vdd-l10-l11-l12-l13-supply = <&vph_pwr>; vdd_l10_l11_l12_l13-supply = <&vph_pwr>;
vreg_s4_1p8: s4 { vreg_s4_1p8: s4 {
regulator-min-microvolt = <1728000>; regulator-min-microvolt = <1728000>;
...@@ -56,8 +56,8 @@ vreg_s4_1p8: s4 { ...@@ -56,8 +56,8 @@ vreg_s4_1p8: s4 {
}; };
vreg_s5_1p35: s5 { vreg_s5_1p35: s5 {
regulator-min-microvolt = <>; regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <>; regulator-max-microvolt = <1352000>;
}; };
vreg_l1_1p3: l1 { vreg_l1_1p3: l1 {
......
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