Commit f9fa153e authored by David S. Miller's avatar David S. Miller

[TG3]: Two more PHY bug workaround, plus fix DMA test on big-endian.

parent 8c9383c4
...@@ -678,6 +678,18 @@ static int tg3_phy_reset(struct tg3 *tp, int force) ...@@ -678,6 +678,18 @@ static int tg3_phy_reset(struct tg3 *tp, int force)
return err; return err;
out: out:
if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
}
if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
tg3_writephy(tp, 0x1c, 0x8d68);
tg3_writephy(tp, 0x1c, 0x8d68);
}
tg3_phy_set_wirespeed(tp); tg3_phy_set_wirespeed(tp);
return 0; return 0;
} }
...@@ -6905,6 +6917,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -6905,6 +6917,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
(tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
/* Only 5701 and later support tagged irq status mode. /* Only 5701 and later support tagged irq status mode.
* Also, 5788 chips cannot use tagged irq status. * Also, 5788 chips cannot use tagged irq status.
* *
...@@ -7407,8 +7425,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp) ...@@ -7407,8 +7425,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
u32 val; u32 val;
tg3_read_mem(tp, 0x2100 + (i*4), &val); tg3_read_mem(tp, 0x2100 + (i*4), &val);
if (val != p[i]) { if (le32_to_cpu(val) != p[i]) {
printk( KERN_ERR " tg3_test_dma() Card buffer currupted on write! (%d != %d)\n", val, i); printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
/* ret = -ENODEV here? */ /* ret = -ENODEV here? */
} }
p[i] = 0; p[i] = 0;
......
...@@ -129,6 +129,9 @@ ...@@ -129,6 +129,9 @@
#define CHIPREV_5700_BX 0x71 #define CHIPREV_5700_BX 0x71
#define CHIPREV_5700_CX 0x72 #define CHIPREV_5700_CX 0x72
#define CHIPREV_5701_AX 0x00 #define CHIPREV_5701_AX 0x00
#define CHIPREV_5703_AX 0x10
#define CHIPREV_5704_AX 0x20
#define CHIPREV_5704_BX 0x21
#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
#define METAL_REV_A0 0x00 #define METAL_REV_A0 0x00
#define METAL_REV_A1 0x01 #define METAL_REV_A1 0x01
...@@ -1924,6 +1927,8 @@ struct tg3 { ...@@ -1924,6 +1927,8 @@ struct tg3 {
#define TG3_FLG2_IS_5788 0x00000008 #define TG3_FLG2_IS_5788 0x00000008
#define TG3_FLG2_MAX_RXPEND_64 0x00000010 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
#define TG3_FLG2_TSO_CAPABLE 0x00000020 #define TG3_FLG2_TSO_CAPABLE 0x00000020
#define TG3_FLG2_PHY_ADC_BUG 0x00000040
#define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
u32 split_mode_max_reqs; u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3 #define SPLIT_MODE_5704_MAX_REQ 3
......
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